IP Facts - IP Facts - 3.0 English - PG278

Video Frame Buffer Read and Video Frame Buffer Write v3.0 LogiCORE IP Product Guide (PG278)
Document ID
PG278
Release Date
2025-11-20
Version
3.0 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 AMD Versal™ Adaptive SoC, AMD UltraScale+™ Families, AMD UltraScale™ Families, AMD Zynq™ 7000 SoC, 7 series

AMD Versal™ AI Edge Series Gen 2 and AMD Versal™ Prime Series Gen 2 series (tile mode)
Supported User Interfaces AXI4-Master, AXI4-Lite, AXI4-Stream 2
Resources
Read
Performance and Resource Utilization for Video Frame Buffer Read web page
Write
Performance and Resource Utilization for Video Frame Buffer Write web page
Provided with Core
Design Files Not Provided
Example Design Yes
Test Bench Not Provided
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Encrypted RTL
Supported S/W Driver 3 Standalone Linux DMA Controller
Tested Design Flows 4
Design Entry AMD Vivado™ Design Suite
Simulation For supported simulators, see Vitis Software Platform Release Notes (UG1742).
Synthesis VivadoSynthesis
Support
Release Notes and Known Issues Master Answer Record
Read
68764
Write
68765
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the AMD Vivado™ IP catalog.

  2. Video protocol as defined in the Video IP: AXI Feature Adoption section of Vivado Design Suite: AXI Reference Guide (UG1037).

  3. Linux OS and driver support information is available from the Linux Video Frame Buffer Read Driver Page and Linux Video Frame Buffer Write Driver Page.
  4. For the supported versions of third-party tools, see Vitis Software Platform Release Notes (UG1742).