Core Behavior with EOL and SOF Signals - 3.0 English - PG278

Video Frame Buffer Read and Video Frame Buffer Write LogiCORE IP Product Guide (PG278)

Document ID
PG278
Release Date
2025-05-29
Version
3.0 English

As discussed in Product Specification, the AXI4-Stream video streaming interface for frame buffer read and write cores includes two flags, tlast and tuser, which are used to identify specific pixels in the video stream.

The tlast signal, also known as the end of line (EOL), marks the last valid pixel of each line. This EOL pulse is one valid transaction wide and must align with the last pixel of a scanline. The tuser signal, referred to as the start of frame (SOF), designates the first valid pixel of a frame. The SOF pulse is also one valid transaction wide and must coincide with the first pixel of the frame, serving as a frame synchronization signal. These EOL and SOF flags are essential for identifying pixel locations on the AXI4-Stream interface, as there are no sync or blank signals. The frame buffer write core maintains internal registers to track the pixels received per line and the lines received per video frame. The behavior of frame buffer write in case of early or late EOL and SOF flags is explained below, assuming tvalid is high when these events occur.

Early EOL
When the EOL signal is asserted prematurely, the core disregards the EOL and continues to receive data until the pixel count per line reaches the frame width specified in the configuration register at offset 0x0010. After receiving the next EOL pulse, the core will reset the pixel count register one cycle later.
Late EOL
If the EOL signal is delayed, the core will ignore any data received after the pixel count per line reaches the frame width set in the configuration register, until the EOL signal is asserted.
Early SOF
When the SOF signal is asserted early, the core initiates the internal line count and pixel count per line, and begins to receive any data arriving on the data bus.
Late SOF
If the SOF signal is asserted late, the core will ignore any data received on the data bus once the internal line count reaches the frame height specified in the configuration register at offset 0x0018, until the SOF signal is asserted.