The following table summarizes the signals, which are either shared by, or not part of the dedicated AXI4-Stream, memory mapped AXI4 data, or AXI4-Lite control interfaces.
| Signal Name | I/O | Width | Description |
|---|---|---|---|
| ap_clk | I | 1 | Video core clock |
| ap_rst_n | I | 1 | Video core active-Low clock enable |
| interrupt | O | 1 | Interrupt Request Pin |
| field_id | O (Frame Buffer Read) | 1 | Field polarity (only available when interlaced support is selected) |
| I (Frame Buffer Write) | |||
| sync_eol 1 | O (Frame Buffer Write) | 1 | End of lines synchronization pulse |
| sync_eof 1 | O (Frame Buffer Write) | 1 | End of frame synchronization pulse |
| partial_frm_wr_done | O (Frame Buffer Write) | 1 | Partial frame synchronization signal |
|
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The ap_clk and ap_rst_n signals are shared between the core, the
AXI4-Stream, memory mapped AXI4 data
interface, and the AXI4-Lite control interface.