This chapter contains information about the example design provided in the AMD Vivado™ Design Suite.
This following section contains steps for running the HBM controller simulations using the AMD Vivado™ HBM Example Design. Simulation is supported with the Verilog Compiler Simulator (VCS), Incisive Enterprise Simulator (IES), and Mentor Graphics Questa Advanced Simulator. For a list of known issues, see AR 69267 for the AXI HBM Controller.