SYSREF Signal Requirements - SYSREF Signal Requirements - 2.6 English - PG269

The SYSREF signal is the timing reference for the system and must therefore be handled correctly to ensure it does not degrade the synchronization. This signal has the following requirements.

1. SYSREF must be a high-quality, free-running, low-jitter signal, to allow it to be captured consistently by the analog sample clock. See the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) for the SYSREF requirements.
2. The SYSREF frequency must meet the following requirements:
   1. If synchronizing RF-ADC and RF-DAC tiles with different sample frequencies, the frequency must be an integer submultiple of:

      GCD(DAC_Sample_Rate/16, ADC_Sample_Rate/16)

   2. SYSREF must also be an integer submultiple of all PL clocks that sample it. This is to ensure the periodic SYSREF is always sampled synchronously.
   3. Less than 10 MHz.
3. SYSREF must be safely captured by the PL, before passing to the core:
   1. Setup/hold of PL_SysRef to PL_clock must be handled as part of the user design.
   2. Clock generation on the PCB can be used to facilitate this, if supported.
4. Analog SYSREF and PL SYSREF must be the same frequency and have a constant phase relationship. If deterministic latency is required, the analog SYSREF and PL SYSREF must keep the same phase difference over reset to reset cycles.
5. For MTS synchronization, which covers both divider phase sync and FIFO latency sync, the analog SYSREF and PL SYSREF must be a continuous clock for the duration of the MTS procedure. It can be either AC-coupled or DC-coupled. The SYSREF signals can be shut down after the completion of the MTS procedure.
   Note: The signals should be turned on and stabilized prior to the MTS function call.
6. If analog SYSREF is being used to synchronize the phase of the DUC/DDC mixer NCOs across multiple AMD Zynq™ UltraScale+™ RFSoCs, then it must be DC-coupled with the ability to generate single or multiple pulse waveforms.