Each RF-DAC tile includes a complete clocking support structure with a PLL and the necessary synchronization logic. Every RF-DAC in a tile has a highly configurable FIFO allowing the internal interconnect logic to have direct high-speed access to the RF-DAC (see the following figure).
Certain functions can only be executed when the RF-DACs in a tile are paired. Even numbered RF-DACs are used for I datapaths and the odd numbered RF-DACs are used for Q datapaths.
All of the available built-in functionality of a tile and each of the RF-DACs in a tile are user programmable. The Zynq UltraScale+ RF Data Converter core configuration screen in the Vivado IDE and the RFdc driver API can be used to configure the digital and analog functionality of the RF-DACs.