Post-Implementation Simulation Speedup Register (0x0100) - Post-Implementation Simulation Speedup Register (0x0100) - 2.6 English

Post-Implementation Simulation Speedup Register (0x0100) - Post-Implementation Simulation Speedup Register (0x0100) - 2.6 English - PG269

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID

PG269

Release Date

2025-05-29

Version

2.6 English

Table 1. Post-Implementation Simulation Speedup Register (0x0100)
Bit	Default Value	Access Type	Description
31:3	-	-	Reserved
2	0	RW	Gen 3/DFE Simulation speed-up. Set high to speed up simulation. This register must not be set in hardware.
1	-	-	Reserved
0	0	RW	Simulation speed-up for post-implementation simulations. Set High to speed up post-implementation simulations. This register must not be set in hardware.