In the previous MTS implementation section, certain API is used to gate
the analog SYSREF signal, or one-shot analog SYSREF
signal is required when some dynamic events (that is, NCOs frequencies) need to be
updated simultaneously.
With Gen 3/DFE, there are two groups of
real-time signals the dacX_sysref_gate and adcX_sysref_gate that are introduced for analog SYSREF gating on chip.
For single chip use case, these real-time signals can replace the SYSREF gating API. For MTS across multiple RFSoCs, all
related SYSREF gating signals should assert to gate
analog SYSREF input first, waiting for all updates be
armed then deassert simultaneously. Thus, the next raising edge of analog SYSREF will trigger the armed dynamic updates. In this
design, all related SYSREF gating signals must be
well-aligned both inside and outside of AMD Zynq™
UltraScale+™ RFSoCs. With this design, the
SYSREF clock can be AC or DC coupled.