TMR Comparator - TMR Comparator - 1.0 English - PG268

MicroBlaze Triple Modular Redundancy (TMR) Subsystem LogiCORE IP Product Guide (PG268)
Document_ID
PG268
Release_Date
2025-12-09
Version
1.0 English

The I/O signals for the TMR Comparator are listed and described in the following table.

Table 1. TMR Comparator I/O Signals
Signal Name Interface I/O Initial State Description
Clk   I - Clock
TMR_Disable   I - TMR disable
Compare   O 0x0 Comparison result
Comparator Test Interface (C_TEST_COMPARATOR > 0)
Rst   I - Synchronous reset
Test_Comparator   I -

Comparator test interface used to:

  • Trigger status capture on error
  • Clear captured status
  • Inject errors

S_AXIS_TDATA_Test

[C_TEST_AXIS_DATA_WIDTH-1:0]

 AXI4-Stream I - AXI4-Stream TDATA test input
S_AXIS_TLAST_Test AXI4-Stream I - AXI4-Stream TLAST test input
S_AXIS_TVALID_Test AXI4-Stream I - AXI4-Stream TVALID test input
S_AXIS_TREADY_Test AXI4-Stream O 0 AXI4-Stream TREADY test output

M_AXIS_TDATA_Test

[C_TEST_AXIS_DATA_WIDTH-1:0]

 AXI4-Stream O 0x0 AXI4-Stream TDATA test output
M_AXIS_TLAST_Test AXI4-Stream O 0 AXI4-Stream TLAST test output
M_AXIS_TVALID_Test AXI4-Stream O 0 AXI4-Stream TVALID test output
M_AXIS_TREADY_Test AXI4-Stream I - AXI4-Stream TREADY test input
Discrete Interface (C_INTERFACE = 0)
Discreten[C_DISCRETE_WIDTH-1:0]   I - Discrete comparison inputs (n = 1-3)(1)
Discrete   I - Discrete voter input(2)
LMB Interface (C_INTERFACE = 1)
LMBn_* (see the following table) LMB I - LMB comparison inputs (n = 1-3)(1)
LMB_* (see the following table) LMB I - LMB voter input(2)
Block RAM Interface (C_INTERFACE = 2)
BRAMn_* (see Table 3) Block RAM I - block RAM comparison inputs (n = 1-3)(1)
BRAM_* (see Table 3) Block RAM I - block RAM voter input(2)
AXI4 and AXI4-Lite Interface (C_INTERFACE = 3, 8, 15 or 17)
S_AXIn_* (see Table 4) AXI4 I - S_AXI comparison inputs (n = 1-3)(1)
M_AXI_* (see Table 4) AXI4 I - M_AXI voter input(2)
AXI4-Stream Master Interface (C_INTERFACE = 4)
S_AXISn_* (see Table 5) AXI4-Stream I - S_AXIS comparison inputs (n = 1-3)(1)
M_AXIS_* (see Table 5) AXI4-Stream I - M_AXIS voter input(2)
AXI4-Stream Slave Interface (C_INTERFACE = 5)
M_AXISn_* (see Table 5) AXI4-Stream I - M_AXIS comparison inputs (n = 1-3)(1)
S_AXIS_* (see Table 5) AXI4-Stream I - S_AXIS voter input(2)
ACE Interface (C_INTERFACE = 6 or 17)
S_AXIn_* (see Table 4) ACE I - S_ACE comparison inputs (n = 1-3)(1)
M_AXI_* (see Table 4) ACE I - M_ACE voter input(2)
Trace Interface (C_INTERFACE = 7)
Tracen_* (see Table 6) Trace I - Trace comparison inputs (n = 1-3)(1)
Interrupt Interface (C_INTERFACE = 9 or 18)
IRQn Interrupt I - IRQ input (n = 1-3)(1), Unused
IRQn_Address Interrupt I - IRQ address input (n = 1-3)(1), Unused
IRQn_Ack Interrupt I - IRQ acknowledge input (n = 1-3)(1)
IRQ Interrupt I - IRQ voter input(2)
IRQ_Address Interrupt I - IRQ address voter input(2)
IRQ_Ack Interrupt I - IRQ acknowledge voter input, Unused(2)
IO Bus Interface (C_INTERFACE = 10)
IOn_* (see Table 7) IOBUS I - IO comparison inputs (n = 1-3)(1)
IO_* (see Table 7) IOBUS I - IO voter input(2)
GPIO Interface (C_INTERFACE = 11)
GPIOn_* (see Table 8) GPIO I - GPIO comparison inputs (n = 1-3)(1)
GPIO_* (see Table 8) GPIO I - GPIO voter input(2)
UART Interface (C_INTERFACE = 12)
UARTn_* (see Table 9) UART I - UART comparison inputs (n = 1-3)(1)
UART_* (see Table 9) UART I - UART voter input(2)
Block RAM Master Interface (C_INTERFACE = 13)
M_BRAMn_* (see Table 3) block RAM I - M_BRAM comparison inputs (n = 1-3)(1)
S_BRAM_* (see Table 3) block RAM I - S_BRAM voter input(2)
LMB Slave Interface (C_INTERFACE = 14)
S_LMBn_* (see the following table) LMB I - S_LMB comparison inputs (n = 1-3)(1)
S_LMB_* (see the following table) LMB I - S_LMB voter input(2)
IIC Interface (C_INTERFACE = 19)
IICn_* (see Table 10) IIC I - IIC comparison inputs (n = 1-3)(1)
IIC_* (see Table 10) IIC I - IIC voter input(2)
  1. The third interface is only enabled when C_TMR is set to 1.
  2. Only enabled when C_VOTER_CHECK is set to 1.

Common interface signals are listed in the following tables.

Table 2. LMB Interface Input Signals
Signal Name Suffix Interface Description
ABus[0:C_LMB_AWIDTH-1] LMB, S_LMB unused Address Bus
Prot[0:1] LMB, S_LMB unused Protection Bits
WriteDBus[0:C_LMB_DWIDTH-1] LMB, S_LMB unused Data Write Bus
AddrStrobe LMB, S_LMB unused Address Strobe
ReadStrobe LMB, S_LMB unused Read Strobe
WriteStrobe LMB, S_LMB unused Write Strobe
BE[0:C_LMB_DWIDTH/8-1] LMB, S_LMB unused Byte Enable
DBus[0:C_LMB_DWIDTH-1] LMB unused, S_LMB Data Read Bus
Ready LMB unused, S_LMB Ready
Wait S_LMB only Wait
UE S_LMB only Uncorrectable Error
CE S_LMB only Correctable Error
Table 3. BRAM Interface Input Signals
Signal Name Suffix Interface Description
Rst Unused Reset
Clk Unused Clock
Addr block RAM, M_BRAM unused Address
EN block RAM, M_BRAM unused Enable
WE block RAM, M_BRAM unused Write Enable
Dout block RAM only Data out
Din M_BRAM only Data in
Table 4. AXI4, AXI4-Lite and ACE Input Interface Signals
Signal Name Suffix Interface Description
AWID AXI4, ACE Write Address ID
AWADDR AXI4, AXI4-Lite, ACE Write Address
AWLEN AXI4, ACE Write Address Length
AWSIZE AXI4, ACE Write Address Size
AWBURST AXI4, ACE Write Address Burst
AWLOCK AXI4, ACE Write Address Lock
AWCACHE AXI4, ACE Write Address Cache
AWPROT AXI4, ACE Write Address Protection
AWQOS AXI4, ACE Write Address QoS
AWVALID AXI4, AXI4-Lite, ACE Write Address Valid
AWREADY Unused Write Address Ready
AWUSER AXI4, AXI4-Lite, ACE Write Address User bits
AWDOMAIN ACE Write Address Domain
AWSNOOP ACE Write Address Transaction Type
AWBAR ACE Write Address Barrier
WDATA AXI4, AXI4-Lite, ACE Write Data
WSTRB AXI4, AXI4-Lite, ACE Write Strobes
WLAST AXI4, ACE Write Last
WVALID AXI4, AXI4-Lite, ACE Write Valid
WREADY Unused Write Ready
WUSER AXI4, AXI4-Lite, ACE Write User bits
WACK ACE Write Acknowledge
BRESP Unused Write Response
BID Unused Write Response ID
BVALID Unused Write Response Valid
BREADY AXI4, AXI4-Lite, ACE Write Response Ready
BUSER Unused Write Response User bits
ARID AXI4, ACE Read Address ID
ARADDR AXI4, AXI4-Lite, ACE Read Address
ARLEN AXI4, ACE Read Address Length
ARSIZE AXI4, ACE Read Address Size
ARBURST AXI4, ACE Read Address Burst
ARLOCK AXI4, ACE Read Address Lock
ARCACHE AXI4, ACE Read Address Cache
ARPROT AXI4, ACE Read Address Protection
ARQOS AXI4, ACE Read Address QoS
ARVALID AXI4, AXI4-Lite, ACE Read Address Valid
ARREADY Unused Read Address Ready
ARUSER AXI4, AXI4-Lite, ACE Read Address User bits
ARDOMAIN ACE Read Address Domain
ARSNOOP ACE Read Address Transaction Type
ARBAR ACE Read Address Barrier
RID Unused Read ID
RDATA Unused Read Data
RRESP Unused Read Response
RLAST AXI4, ACE Read Last
RVALID AXI4, AXI4-Lite, ACE Read Valid
RREADY Unused Read Ready
RUSER Unused Read User bits
RACK ACE Read Acknowledge
ACVALID Unused Snoop Address Valid
ACADDR Unused Snoop Address
ACSNOOP Unused Snoop Address Transaction Type
ACPROT Unused Snoop Address Protection Type
ACREADY ACE Snoop Address Ready
CRVALID ACE Snoop Response Valid
CRRESP ACE Snoop Response
CRREADY Unused Snoop Response Ready
CDVALID ACE Snoop Data Valid
CDDATA ACE Snoop Data
CDLAST ACE Snoop Data Last
CDREADY Unused Snoop Data Ready
Table 5. AXI4-Stream Input Interface Signals
Signal Name Suffix Interface Description
TLAST S_AXIS Transfer Last
TDATA S_AXIS Transfer Data
TVALID S_AXIS Transfer Valid
TREADY M_AXIS Transfer Ready
TSTRB S_AXIS Transfer Strobe
TKEEP S_AXIS Transfer Keep
TID S_AXIS Transfer ID
TDEST S_AXIS Transfer Destination
TUSER S_AXIS Transfer User bits
Table 6. Trace Input Interface Signals
Signal Name Suffix Interface Description
Valid_Instr C_TRACE_SIZE = 0,1,2 Valid instruction on trace port
Instruction C_TRACE_SIZE = 0 Instruction code
PC C_TRACE_SIZE = 0 Program counter
Reg_Write C_TRACE_SIZE = 0,1,2 Instruction writes to the register file
Reg_Addr C_TRACE_SIZE = 0,1,2 Destination register address
MSR_Reg C_TRACE_SIZE = 0 Machine status register
PID_Reg C_TRACE_SIZE = 0 Process identifier register
New_Reg_Value C_TRACE_SIZE = 0,1,2 Destination register update value
Exception_Taken C_TRACE_SIZE = 0 Instruction results in taken exception
Exception_Kind C_TRACE_SIZE = 0 Exception type
Jump_Taken C_TRACE_SIZE = 0 Branch instruction evaluated true
Jump_Hit C_TRACE_SIZE = 0 Branch Target Cache hit
Delay_Slot C_TRACE_SIZE = 0 Instruction is in delay slot of taken branch
Data_Access C_TRACE_SIZE = 0,2 Valid D-side memory access
Data_Address C_TRACE_SIZE = 0,2 Address for D-side memory access
Data_Write_Value C_TRACE_SIZE = 0,2 Value for D-side memory access
Data_Byte_Enable C_TRACE_SIZE = 0,2 Byte enables for D-side memory access
Data_Read C_TRACE_SIZE = 0,2 D-side memory access is read
Data_Write C_TRACE_SIZE = 0,2 D-side memory access is write
DCache_Req C_TRACE_SIZE = 0 Data memory address within D-Cache
DCache_Hit C_TRACE_SIZE = 0 Data memory address present
DCache_Rdy C_TRACE_SIZE = 0 Data memory access completed
DCache_Read C_TRACE_SIZE = 0 D-Cache request is a read
ICache_Req C_TRACE_SIZE = 0 Instruction memory address within I-Cache
ICache_Hit C_TRACE_SIZE = 0 Instruction memory address present
ICache_Rdy C_TRACE_SIZE = 0 Instruction memory access completed
OF_PipeRun C_TRACE_SIZE = 0 Pipeline advance for Decode stage
EX_PipeRun C_TRACE_SIZE = 0 Pipeline advance for Execute stage
MEM_PipeRun C_TRACE_SIZE = 0 Pipeline advance for Memory stage
MB_Halted C_TRACE_SIZE = 0 Pipeline is halted by debug
Table 7. IOBUS Input Interface Signals
Signal Name Suffix Interface Description
Addr_Strobe IO Address Strobe
Read_Strobe IO Read Strobe
Write_Strobe IO Write Strobe
Address IO Address
Prot IO Protection Bits
Byte_Enable IO Byte Enable
Write_Data IO Write Data
Read_Data Unused Read Data
Ready Unused Ready
Table 8. GPIO Input Interface Signals
Signal Name Suffix Interface Description
GPO GPIO General Purpose Output
GPT GPIO General Purpose Tristate
GPI Unused General Purpose Input
Table 9. UART Input Interface Signals
Signal Name Suffix Interface Description
RX Unused Serial Input
TX UART Serial Output
RTSn UART Request to Send
CTSn Unused Clear to Send
DTRn UART Data Terminal Ready
DSRn Unused Data Set Ready
BAUDOUTn UART Baud Out
RCLK Unused Receiver Clock
XIN Unused External Crystal Input
XOUT UART External Crystal Output
DCDn Unused Data Carrier Detect
DDIS UART Driver Disable
OUT1n UART User Controlled Output 1
OUT2n UART User Controlled Output 2
TXRDYn UART Transmitter DMA Control Signal
RXRDYn UART Receiver DMA Control Signal
RI Unused Ring Indicator
Table 10. IIC Input Interface Signals
Signal Name Suffix Interface Description
scl_i Unused Serial Clock Line input
scl_o IIC Serial Clock Line Output
scl_t IIC Serial Clock Line tristate
sda_i Unused Serial Data input
sda_o IIC Serial Data output
sda_t IIC Serial Data tristate