SEM Interrupt Mask Register (SEMIMR) - 1.0 English - PG268

MicroBlaze Triple Modular Redundancy (TMR) Subsystem LogiCORE IP Product Guide (PG268)
Document ID
PG268
Release Date
2025-12-09
Version
1.0 English

The SEM interrupt mask register enables interrupt generation from signals from the TMR SEM interface. This is a write only register.Issuing a read request generates the read acknowledgment with zero data. The register bit assignment is shown in the following table and described in Table 2. The register is only implemented if C_SEM_INTERFACE is set to 1.

Table 1. SEM Interrupt Mask Register (SEMIMR)
Reserved DS DO ESS UNC INJ CLA CORR OBS INI HB HBWE
31 11 10 9 8 7 6 5 4 3 2 1 0
Table 2. SEM Interrupt Mask Register Bit Definitions
Bits Name Access Reset Value Description
31-11 Reserved N/A 0 Reserved
10 Diagnostic Scan R 0 The SEM Diagnostic Scan input causes an interrupt.
9 Detect Only R 0 The SEM Detect Only input causes an interrupt.
8 Essential R 0 The SEM Essential input causes an interrupt.
7 Uncorrectable R 0 The SEM Uncorrectable input causes an interrupt.
6 Injection R 0 The SEM Injection input causes an interrupt.
5 Classification R 0 The SEM Classification input causes an interrupt.
4 Correction R 0 The SEM Correction input causes an interrupt.
3 Observation R 0 The SEM Observation input causes an interrupt.
2 Initialization R 0 The SEM Initialization input causes an interrupt.
1 Heartbeat R 0 The SEM Heartbeat input causes an interrupt.
0 Heartbeat Watchdog Expired R 0

The SEM heartbeat watchdog causes an interrupt:

0 = No interrupt.

1 = An interrupt occurs when the watchdog expires.