These documents provide supplemental material useful with this guide:
- AXI Timebase Watchdog Timer LogiCORE IP Product Guide (PG128)
- AMBA AXI and ACE Protocol Specification (Arm IHI 0022E)
- 7 Series FPGAs Configuration User Guide (UG470)
- MicroBlaze Processor Reference Guide (UG984)
- Soft Error Mitigation Controller LogiCORE IP Product Guide (PG036)
- UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)
- AXI UART Lite LogiCORE IP Product Guide (PG142)
- Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
- Vivado Design Suite User Guide: Designing with IP (UG896)
- Vivado Design Suite User Guide: Getting Started (UG910)
- Vivado Design Suite User Guide: Logic Simulation (UG900)
- Vivado Design Suite User Guide: Programming and Debugging (UG908)
- AXI Interconnect LogiCORE IP Product Guide (PG059)
- LMB BRAM Interface Controller LogiCORE IP Product Guide (PG112)
- The following lists additional resources you can access directly using the provided URLs: Brigham Young University, Configurable Computing Lab
- Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)