The status register contains the status of the receive and transmit data FIFOs, and when interrupt is enabled. This is a read only register. If a write request is issued to the status register it does nothing but generate a write acknowledgment. The register bit assignment is shown in the following table and described in Table 2. The register is only implemented if C_INTERFACE is set to 0.
| Reserved | MON_STATUS | ||
|---|---|---|---|
| 31 | 5 | 4 | 0 |
| Bits | Name | Access | Reset Value | Description |
|---|---|---|---|---|
| 31-5 | Reserved | N/A | 0 | Reserved |
| 4 | Interrupt Enabled | R | 0 |
Indicates that interrupt is enabled. 0 = Interrupt is disabled 1 = Interrupt is enabled |
| 3 | TX FIFO Full | R | 0 |
Indicates if the transmit FIFO is full. 0 = Transmit FIFO is not full 1 = Transmit FIFO is full |
| 2 | TX FIFO Empty | R | 1 |
Indicates if the transmit FIFO is empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty |
| 1 | RX FIFO Full | R | 0 |
Indicates if the receive FIFO is full. 0 = Receive FIFO is not full 1 = Receive FIFO is full |
| 0 | RX FIFO Valid Data | R | 0 |
Indicates if the receive FIFO has valid data. 0 = Receive FIFO is empty 1 = Receive FIFO has valid data |