| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family(1) | AMD UltraScale+™ , AMD UltraScale™ , AMD Zynq™ 7000 SoC, 7 series, AMD Versal™ devices |
| Supported User Interfaces |
ACE, AXI4-Lite, AXI4-Stream, Block RAM, Dynamic Reconfiguration Port (DRP), GPIO, Local Memory Bus (LMB), Interrupt, UART |
| Resources | Performance and Resource Use web page |
| Provided with Subsystem | |
| Design Files | RTL |
| Example Design | VHDL |
| Test Bench | Not Provided |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | Not Provided |
| Supported S/W Driver(2) | Standalone |
| Tested Design Flows(3) | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | AMD Vivado™ Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 68483 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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