Example Design - 1.0 English - PG268

MicroBlaze Triple Modular Redundancy (TMR) Subsystem LogiCORE IP Product Guide (PG268)

Document ID
PG268
Release Date
2025-12-09
Version
1.0 English

This chapter contains information about the example design provided in the AMD Vivado™ Design Suite.

The TMR Manager has a system-level example design, which includes the other four IP cores. This example consists of a Vivado IPI Block Design, with a MicroBlaze TMR subsystem that closely resembles the design in Figure 1.

Important: The example design is currently only available for the boards AC701, KC705, KCU105, VC707, VC709, VCU108, VCU110, and VCU118. If any other board is selected in the project from which the example is generated, the example uses the KCU105 board instead.