Control Register (CR) - Control Register (CR) - 1.0 English - PG268

MicroBlaze Triple Modular Redundancy (TMR) Subsystem LogiCORE IP Product Guide (PG268)
Document_ID
PG268
Release_Date
2025-12-09
Version
1.0 English

The control register determines how the TMR manager handles any detected faults. This is write only register. Issuing a read request to the control register generates the read acknowledgment with zero data. The register bit assignment is shown in the following table and described in Table 2.

Table 1. Control Register (CR)
Reserved BFO BB BFR RIR MAGIC2 MAGIC1
31 20 19 18 17 16 15 8 7 0
Table 2. Control Register Bit Definitions
Bits Name Access Reset Value Description
31-20 Reserved N/A 0 Reserved
19 Block Fatal Output W 0

Determine if the Fatal output signal is blocked:

0 = Fatal output signal is set on fatal error.

1 = Block Fatal output signal.
18 Block Break W 0

Determine if Break signal is sent to MicroBlaze:

0 = Break signal is sent.

1 = Block break signal.
17 Block Fatal Reset W 0

Determine if a fatal error causes a reset:

0 = Reset on fatal error.

1 = Block reset on fatal error.
16 Recover Is Reset W 0

Treat MicroBlaze™ Recover signal as reset:

0 = No reset on recover.

1 = Reset on recover.
15-8 Magic Byte 2 W 0x00

Magic Byte 2

Must be set to the value of parameter C_MAGIC2 to:

  • Enable masking of comparators defined in CMR0-1
  • Allow the BFR bit to block reset on fatal error
  • Allow the BFO bit to block fatal output signal
  • Reset failing status by writing any value to RFSR
7-0 Magic Byte 1 W 0x00

Magic Byte 1

Must be set to the value of parameter C_MAGIC1 to:

  • Allow the RIR bit to generate reset on recovery
  • Allow the BB bit to block the break signal
  • Clear FFR by writing any value