Break Delay Initialization Register (BDIR) - 1.0 English - PG268

MicroBlaze Triple Modular Redundancy (TMR) Subsystem LogiCORE IP Product Guide (PG268)
Document ID
PG268
Release Date
2025-12-09
Version
1.0 English

This register contains the counter defining the delay from a fatal error has been detected until the MicroBlaze break signal is set to 1. The register definition is shown in the following table. The register is write-only. Issuing a read request generates the read acknowledgment with zero data. The register is only implemented if C_BRK_DELAY_WIDTH is greater than 0, and the initial value after reset is determined by C_BRK_DELAY_RST_VALUE.

Table 1. Break Delay Initialization Register (BDIR)
Reserved Break Delay
31 C_BRK_DELAY_WIDTH C_BRK_DELAY_WIDTH-1 0