VCU_PLL_CLK_HI - VCU_PLL_CLK_HI - 2026.1 English - PG252

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document_ID
PG252
Release_Date
2026-09-03
Version
2026.1 English
Table 1. VCU_PLL_CLK_HI
Address Offset Width Type Reset Value Description
0x41034 32 RO 0x0 This register describes value of PLL clock
Table 2. VCU_PLL_CLK_HI Bit Field Information
Field Name Bits Type Reset Value Definition
VCU_PLL_CLK_HI [31:0] RO 0x0

Reports the integer value of PLL clock

frequency as set in the Vivado block

design. Each unit is 10 kHz. Default: 33.33MHz