Performance - 2025.1 English - PG252

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document ID
PG252
Release Date
2025-05-29
Version
2025.1 English

System Throughput

The following table shows memory controller performance for running a 4kp60, 4:2:2, 10-bit decode-display pipeline. These throughput numbers are based on x8 configuration of the controller at 2133 DRAM speed.

Table 1. Memory Controller Performance
Bandwidth Decoder port 0 Decoder port 1 Display Video traffic generator in PL
Read bandwidth 1879.78 MBps 1913.62 MBps 1328.09 MB/s 950.72 MBps
Write bandwidth 895.32 MBps 792.01 MBps N/A N/A

The following table summarizes performance in decoded images/sec for decoding a 4kp60 video stream, 4:2:2, 10-bit, using four B-frames.

Table 2. Decoding Performance
Speed Frame-rate Decode Only Frame-rate Decode + Display
X8 93 frames/sec 74 frames/sec
X16 89 frames/sec 70 frames/sec

VCU DDR4 Controller Latency

Note: These numbers do not include the latency information from the interconnect in the fabric. For more information, see the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150).

Latency number for the access times in "VCU DDR4 Controller" is 130 ns on SODIMM MTA8ATF51264HZ-2G6B1 @ 2400.