The VCU Sync IP core is designed to act as a fence IP between the Video DMA and VCU IPs. It is used in video applications that require ultra-low latencies. The Sync IP performs AXI-transaction-level tracking so that the producer and consumer can be synchronized at the granularity of AXI transactions instead of the granularity of the video buffer level. The Sync IP element is responsible for synchronizing buffers between the capture DMA and the VCU encoder. The Sync IP can only synchronize between capture DMA and VCU encoder.
While the capture element is writing into the DRAM, the capture hardware writes video buffers in raster scan order and the Sync IP monitors the buffer level. It allows the encoder to read input buffer data, if the requested data is already written by the DMA; otherwise, it blocks the encoder until the DMA completes its writes. On the decoder side, the VCU decoder writes the decoded video buffer into the DRAM in block raster scan order and the display reads data in raster scan order.
1: The frame buffer writes into the memory. In encoder mode, the Sync IP snoops the transactions.
2: The VCU encoder reads the transactions. The Sync IP only allows reads when the frame buffer has completed the writes to those sections of the memory.
3: The VCU encoder writes the compressed video stream back to DRAM.
4: The VCU decoder reads the compressed video stream from DRAM.
5: The VCU decoder writes back decoded frames into DRAM.
6: The display reads decoded frames after half the frame is written by the VCU decoder.