Overview - 2024.1 English - PG252

The AMD UltraScale+ architecture includes the DDR4 SDRAM cores. These cores provide solutions for interfacing with these SDRAM memory types. Both a complete Memory Controller and a physical layer only solution are supported. This controller is optimized for the VCU traffic patterns, specifically the decoder accesses to memory. The UltraScale+ architecture for the DDR4 cores are organized in the following high-level blocks:

Controller

The controller accepts burst transactions from the user interface and generates transactions to and from the SDRAM. The controller takes care of the SDRAM timing parameters and refresh. It coalesces write and read transactions to reduce the number of dead cycles involved in turning the bus around. The controller also reorders commands to improve the usage of the data bus to the SDRAM.

Physical Layer

The physical layer provides a high-speed interface to the SDRAM. This layer includes the hard blocks inside the FPGA and the soft blocks calibration logic necessary to ensure optimal timing of the hard blocks interfacing to the SDRAM. The application logic is responsible for all SDRAM transactions, timing, and refresh.

These hard blocks include:

• Data serialization and transmission
• Data capture and deserialization
• High-speed clock generation and synchronization
• Coarse and fine delay elements per pin with voltage and temperature tracking

The soft blocks include:

Memory Initialization

The calibration modules provide a JEDEC®-compliant initialization routine for the particular memory type. The delays in the initialization process can be bypassed to speed up simulation time, if desired.

Calibration

The calibration modules provide a complete method to set all delays in the hard blocks and soft IP to work with the memory interface. Each bit is individually trained and then combined to ensure optimal interface performance. Results of the calibration process are available through the AMD debug tools. After completion of calibration, the PHY layer presents raw interface to the SDRAM.