Introduction - Introduction - 2026.1 English - PG252

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document_ID
PG252
Release_Date
2026-09-03
Version
2026.1 English

The VCU Sync IP core is a video buffer fence IP designed to be used with the AMD Zynq™ UltraScale+™ MPSoCs EV series designs. This section provides information about using, customizing, and simulating the VCU Sync IP core for Zynq UltraScale+ MPSoCs. It also describes the architecture and provides details on customizing and interfacing to the VCU.