Applications that use the decoder must connect all the decoder ports (ports beginning with m_axi_dec). The following table shows the decoder block AXI4 master interface ports.
| Name | Width | Direction | Description |
|---|---|---|---|
| vcu_pl_dec_araddr0/1 | 44 | Output | AXI4 ARADDR signal |
| vcu_pl_dec_arburst0/1 | 2 | Output | AXI4 ARBURST signal |
| vcu_pl_dec_arid0/1 | 4 | Output | AXI4 ARID signal |
| vcu_pl_dec_arlen0/1 | 8 | Output | AXI4 ARLEN signal |
| pl_vcu_dec_arready0/1 | 1 | Input | AXI4 ARREADY signal |
| vcu_pl_dec_arsize0/1 | 3 | Output | AXI4 ARSIZE signal |
| vcu_pl_dec_arvalid0/1 | 1 | Output | AXI4 ARVALID signal |
| vcu_pl_dec_awaddr0/1 | 44 | Output | AXI4 AWADDR signal |
| vcu_pl_dec_awburst0/1 | 2 | Output | AXI4 AWBURST signal |
| vcu_pl_dec_awid0/1 | 4 | Output | AXI4 AWID signal |
| vcu_pl_dec_awlen0/1 | 8 | Output | AXI4 AWLEN signal |
| pl_vcu_dec_awready0/1 | 1 | Input | AXI4 AWREADY signal |
| vcu_pl_dec_awsize0/1 | 3 | Output | AXI4 AWSIZE signal |
| vcu_pl_dec_awvalid0/1 | 1 | Output | AXI4 AWVALID signal |
| pl_vcu_dec_bresp0/1 | 2 | Input | AXI4 BRESP signal |
| vcu_pl_dec_bready0/1 | 1 | Output | AXI4 BREADY signal |
| pl_vcu_dec_bvalid0/1 | 1 | Input | AXI4 BVALID signal |
| pl_vcu_dec_bid0/1 | 4 | Input | AXI4 BID signal |
| pl_vcu_dec_rdata0/1 | 128 | Input | AXI4 RDATA signal |
| pl_vcu_dec_rid0/1 | 4 | Input | AXI4 RID signal |
| pl_vcu_dec_rlast0/1 | 1 | Input | AXI4 RLAST signal |
| vcu_pl_dec_rready0/1 | 1 | Output | AXI4 RREADY signal |
| pl_vcu_dec_rresp0/1 | 2 | Input | AXI4 RRESP signal |
| pl_vcu_dec_rvalid0/1 | 1 | Input | AXI4 RVALID signal |
| vcu_pl_dec_wdata0/1 | 128 | Output | AXI4 WDATA signal |
| vcu_pl_dec_wlast0/1 | 1 | Output | AXI4 WLAST signal |
| pl_vcu_dec_wready0/1 | 1 | Input | AXI4 WREADY signal |
| vcu_pl_dec_wvalid0/1 | 1 | Output | AXI4 WVALID signal |
| vcu_pl_dec_awprot0/1 | 1 | Output | AXI4 AWPROT signal, controlled from System Level Control Register (SLCR) |
| vcu_pl_dec_arprot0/1 | 1 | Output | AXI4 ARPROT signal, controlled from SLCR |
| vcu_pl_dec_awqos0/1 | 4 | Output | AXI4 AWQOS signal, controlled from SLCR |
| vcu_pl_dec_arqos0/1 | 4 | Output | AXI4 ARQOS signal, controlled from SLCR |
| vcu_pl_dec_awcache0/1 | 4 | Output | AXI4 AWCACHE signal, controlled from SLCR |
| vcu_pl_dec_arcache0/1 | 4 | Output | AXI4 ARCACHE signal, controlled from SLCR |
| vcu_pl_dec_arregion0/1 | 4 | Output | AXI Master Region identifier |
| vcu_pl_dec_awregion0/1 | 4 | Output |
AXI Master Region identifier |
| vcu_pl_dec_awlock0/1 | 1 | Output | AXI Master Lock Type Signal port |
| vcu_pl_dec_wstrb0/1 | 16 | Output |
AXI Master Strobe Signal port |
| vcu_pl_dec_arlock0/1 | 1 | Output | AXI Master Lock Type Signal port |