Applications that use the encoder block must connect all encoder ports
(ports with names beginning with m_axi_enc). The
following table shows the list of ports/interfaces of the top-level encoder
block.
| Name | Size (bits) | Dir | Description |
|---|---|---|---|
| Clocks and Resets | |||
| pll_ref_clk | 1 | Input | Reference clock to the VCU PLL from PL |
| m_axi_enc_aclk | 1 | Input | Memory interface Encoder clock |
| m_axi_dec_aclk | 1 | Input | Memory interface Decoder clock |
| s_axi_lite_aclk | 1 | Input | AXI4-Lite clock |
| m_axi_mcu_aclk | 1 | Input | VCU MCU AXI interface clock from PL |
| vcu_resetn | 1 | Input | Active-Low. VCU reset from PL |
| VCU-Interrupt (s_axi_lite_aclk) | |||
| vcu_host_interrupt | 1 | Output | Active-High. Interrupt from VCU to PS |
| VCU Encoder Block, 128-bit AXI Master Interface 0 (m_axi_enc_aclk domain) | |||
| vcu_pl_enc_araddr0 | 44 | Output | AXI Master read address bus for interface 0 |
| vcu_pl_enc_arburst0 | 2 | Output | AXI Master read burst type signal |
| vcu_pl_enc_arid0 | 4 | Output | AXI Master read burst ID for interface 0 |
| vcu_pl_enc_arlen0 | 8 | Output | AXI Master read burst length for interface 0 |
| pl_vcu_enc_arready0 | 1 | Input | AXI Master read address ready for interface 0 |
| vcu_pl_enc_arsize0 | 3 | Output | AXI Master read interface size for interface 0 |
| vcu_pl_enc_arvalid0 | 1 | Output | AXI Master read address valid for interface 0 |
| vcu_pl_enc_awaddr0 | 44 | Output | AXI Master write address for interface 0 |
| vcu_pl_enc_awburst0 | 2 | Output | AXI Master write burst type for interface 0 |
| vcu_pl_enc_awid0 | 4 | Output | AXI Master write burst ID for interface 0 |
| vcu_pl_enc_awlen0 | 8 | Output | AXI Master write burst length for interface 0 |
| pl_vcu_enc_awready0 | 1 | Input | AXI Master write address ready for interface 0 |
| vcu_pl_enc_awsize0 | 3 | Output | AXI Master write burst size for interface 0 |
| vcu_pl_enc_awvalid0 | 1 | Output | AXI Master write address valid for interface 0 |
| pl_vcu_enc_bresp0 | 2 | Input | AXI Master write response for interface 0 |
| vcu_pl_enc_bready0 | 1 | Output | AXI Master write response ready for interface 0 |
| pl_vcu_enc_bvalid0 | 1 | Input | AXI Master write response valid for interface 0 |
| pl_vcu_enc_bid0 | 4 | Input | AXI Master write response ID for interface 0 |
| pl_vcu_enc_rdata0 | 128 | Input | AXI Master read data for interface 0 |
| pl_vcu_enc_rid0 | 4 | Input | AXI Master read ID signal for interface 0 |
| pl_vcu_enc_rlast0 | 1 | Input | AXI Master read last signal for interface 0 |
| vcu_pl_enc_rready0 | 1 | Output | AXI Master read ready signal for interface 0 |
| Pl_vcu_enc_rresp0 | 2 | Input | AXI Master read response signal for interface 0 |
| pl_vcu_enc_rvalid0 | 1 | Input | AXI Master read valid signal for interface 0 |
| vcu_pl_enc_wdata0 | 128 | Output | AXI Master write data for interface 0 |
| vcu_pl_enc_wlast0 | 1 | Output | AXI Master write last signal for interface 0 |
| pl_vcu_enc_wready0 | 1 | Input | AXI Master write ready signal for interface 0 |
| vcu_pl_enc_wvalid0 | 1 | Output | AXI Master write valid signal for interface 0 |
| vcu_pl_enc_awprot0 | 3 | Output | AXI Master write protection signal for interface 0, controlled from SLCR |
| vcu_pl_enc_arprot0 | 3 | Output | AXI Master read protection signal for interface 0, controlled from SLCR |
| vcu_pl_enc_awqos0 | 4 | Output | AXI Master write QOS signal for interface 0, controlled from SLCR |
| vcu_pl_enc_arqos0 | 4 | Output | AXI Master read QOS signal for interface 0, controlled from SLCR |
| vcu_pl_enc_awcache0 | 4 | Output | AXI Master write cache signal for interface 0, controlled from SLCR |
| vcu_pl_enc_arcache0 | 4 | Output | AXI Master read cache signal for interface 0, controlled from SLCR |
| VCU Encoder Block, 128-bit AXI Master Interface 0 (m_axi_enc_aclk domain) | |||
| vcu_pl_enc_arregion0 | 4 | Output | AXI Master Region identifier |
| vcu_pl_enc_awregion0 | 4 | Output | AXI Master Region identifier |
| vcu_pl_enc_awlock0 | 1 | Output | AXI Master Lock Type Signal port |
| vcu_pl_enc_wstrb0 | 16 | Output | AXI Master Strobe Signal port |
| vcu_pl_enc_arlock0 | 1 | Output | AXI Master Lock Type Signal port |
| VCU Encoder Block, 128-bit AXI Master Interface 1 (m_axi_enc_aclk domain) | |||
| vcu_pl_enc_araddr1 | 44 | Output | AXI Master read address bus for interface 1 |
| vcu_pl_enc_arburst1 | 2 | Output | AXI Master read burst type signal |
| vcu_pl_enc_arid1 | 4 | Output | AXI Master read burst ID for interface 1 |
| vcu_pl_enc_arlen1 | 8 | Output | AXI Master read burst length for interface 1 |
| pl_vcu_enc_arready1 | 1 | Input | AXI Master read address ready for interface 1 |
| vcu_pl_enc_arsize1 | 3 | Output | AXI Master read interface size for interface 1 |
| vcu_pl_enc_arvalid1 | 1 | Output | AXI Master read address valid for interface 1 |
| vcu_pl_enc_awaddr1 | 44 | Output | AXI Master write address for interface 1 |
| vcu_pl_enc_awburst1 | 2 | Output | AXI Master write burst type for interface 1 |
| vcu_pl_enc_awid1 | 4 | Output | AXI Master write burst ID for interface 1 |
| vcu_pl_enc_awlen1 | 8 | Output | AXI Master write burst length for interface 1 |
| pl_vcu_enc_awready1 | 1 | Input | AXI Master write address ready for interface 1 |
| vcu_pl_enc_awsize1 | 3 | Output | AXI Master write burst size for interface 1 |
| vcu_pl_enc_awvalid1 | 1 | Output | AXI Master write address valid for interface 1 |
| Pl_vcu_enc_bresp1 | 2 | Input | AXI Master write response for interface 1 |
| vcu_pl_enc_bready1 | 1 | Output | AXI Master write response ready for interface 1 |
| pl_vcu_enc_bvalid1 | 1 | Input | AXI Master write response valid for interface 1 |
| pl_vcu_enc_bid1 | 4 | Input | AXI Master write response ID for interface 1 |
| pl_vcu_enc_rdata1 | 128 | Input | AXI Master read data for interface 1 |
| pl_vcu_enc_rid1 | 4 | Input | AXI Master read ID signal for interface 1 |
| pl_vcu_enc_rlast1 | 1 | Input | AXI Master read last signal for interface 1 |
| vcu_pl_enc_rready1 | 1 | Output | AXI Master read ready signal for interface 1 |
| Pl_vcu_enc_rresp1 | 2 | Input | AXI Master read response signal for interface 1 |
| pl_vcu_enc_rvalid1 | 1 | Input | AXI Master read valid signal for interface 1 |
| vcu_pl_enc_wdata1 | 128 | Output | AXI Master write data for interface 1 |
| vcu_pl_enc_wlast1 | 1 | Output | AXI Master write last signal for interface 1 |
| pl_vcu_enc_wready1 | 1 | Input | AXI Master write ready signal for interface 1 |
| vcu_pl_enc_wvalid1 | 1 | Output | AXI Master write valid signal for interface 1 |
| vcu_pl_enc_awprot1 | 3 | Output | AXI Master write protection signal for interface 1, controlled from SLCR |
| vcu_pl_enc_arprot1 | 3 | Output | AXI Master read protection signal for interface 1, controlled from SLCR |
| vcu_pl_enc_awqos1 | 4 | Output | AXI Master write QOS signal for interface 1, controlled from SLCR |
| vcu_pl_enc_arqos1 | 4 | Output | AXI Master read QOS signal for interface 1, controlled from SLCR |
| vcu_pl_enc_awcache1 | 4 | Output | AXI Master write cache signal for interface 1, controlled from SLCR |
| vcu_pl_enc_arcache1 | 4 | Output | AXI Master read cache signal for interface 1, controlled from SLCR |
| VCU Encoder block , 128-bit AXI Master Interface1 | |||
| vcu_pl_enc_arregion1 | 4 | Output | AXI Master Region identifier |
| vcu_pl_enc_awregion1 | 4 | Output | AXI Master Region identifier |
| vcu_pl_enc_awlock1 | 1 | Output | AXI Master Lock Type Signal port |
| vcu_pl_enc_wstrb1 | 16 | Output | AXI Master Strobe Signal port |
| vcu_pl_enc_arlock1 | 1 | Output |
AXI Master Lock Type Signal port |
| VCU Encoder- 32-bit AXI Master MCU Instruction and Data Cache Interface | |||
| vcu_pl_mcu_m_axi_ic_dc_araddr | 44 | Output | AXI Master read address bus for MCU |
| vcu_pl_mcu_m_axi_ic_dc_arburst | 2 | Output | AXI Master read burst type signal |
| vcu_pl_mcu_m_axi_ic_dc_arcache | 4 | Output | AXI Master read cache for MCU |
| vcu_pl_mcu_m_axi_ic_dc_arid | 3 | Output | AXI Master read burst ID for MCU |
| vcu_pl_mcu_m_axi_ic_dc_arlen | 8 | Output | AXI Master read burst length for MCU |
| vcu_pl_mcu_m_axi_ic_dc_arlock | 1 | Output | AXI Master read lock for MCU |
| vcu_pl_mcu_m_axi_ic_dc_arprot | 3 | Output | AXI Master read protection signal for MCU |
| vcu_pl_mcu_m_axi_ic_dc_arqos | 4 | Output | AXI Master read QoS for MCU |
| pl_vcu_mcu_m_axi_ic_dc_arready | 1 | Input | AXI Master read address ready for MCU |
| vcu_pl_mcu_m_axi_ic_dc_arsize | 3 | Output | AXI Master read address size for MCU |
| vcu_pl_mcu_m_axi_ic_dc_arvalid | 1 | Output | AXI Master read address valid for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awaddr | 44 | Output | AXI Master write address for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awburst | 2 | Output | AXI Master write burst type for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awcache | 4 | Output | AXI Master write cache for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awid | 3 | Output | AXI Master write address ID for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awlen | 8 | Output | AXI Master write burst length for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awlock | 1 | Output | AXI Master write lock for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awprot | 3 | Output | AXI Master write protection for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awqos | 4 | Output | AXI Master write QoS for MCU |
| pl_vcu_mcu_m_axi_ic_dc_awready | 1 | Input | AXI Master write address ready signal for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awsize | 3 | Output | AXI Master write burst size signal for MCU |
| vcu_pl_mcu_m_axi_ic_dc_awvalid | 1 | Output | AXI Master write address valid signal for MCU |
| pl_vcu_mcu_m_axi_ic_dc_bid | 3 | Input | AXI Master write response ID for MCU |
| vcu_pl_mcu_m_axi_ic_dc_bready | 1 | Output | AXI Master write response ready signal for MCU |
| pl_vcu_mcu_m_axi_ic_dc_bresp | 2 | Input | AXI Master write response for MCU |
| pl_vcu_mcu_m_axi_ic_dc_bvalid | 1 | Input | AXI Master write response valid signal for MCU |
| pl_vcu_mcu_m_axi_ic_dc_rdata | 32 | Input | AXI Master read data signal for MCU |
| pl_vcu_mcu_m_axi_ic_dc_rid | 3 | Input | AXI Master read ID signal for MCU |
| pl_vcu_mcu_m_axi_ic_dc_rlast | 1 | Input | AXI Master read last signal for MCU |
| vcu_pl_mcu_m_axi_ic_dc_rready | 1 | Output | AXI Master read ready signal for MCU |
| pl_vcu_mcu_m_axi_ic_dc_rresp | 2 | Input | AXI Master read response signal for MCU |
| pl_vcu_mcu_m_axi_ic_dc_rvalid | 1 | Input | AXI Master read valid signal for MCU |
| vcu_pl_mcu_m_axi_ic_dc_wdata | 32 | Output | AXI Master write data signal for MCU |
| vcu_pl_mcu_m_axi_ic_dc_wlast | 1 | Output | AXI Master write last signal for MCU |
| pl_vcu_mcu_m_axi_ic_dc_wready | 1 | Input | AXI Master write ready signal for interface 1 |
| vcu_pl_mcu_m_axi_ic_dc_wstrb | 4 | Output | AXI Master write strobe signal |
| vcu_pl_mcu_m_axi_ic_dc_wvalid | 1 | Output | AXI Master write valid signal for MCU |
| AXI4-Lite Slave Interface (s_axi_lite_aclk domain) | |||
| pl_vcu_awaddr_axi_lite_apb | 20 | Input | AXI4-Lite write address bus |
| pl_vcu_awprot_axi_lite_apb | 3 | Input | AXI4-Lite write protection signal |
| pl_vcu_awvalid_axi_lite_apb | 1 | Input | AXI4-Lite write address valid signal |
| vcu_pl_awready_axi_lite_apb | 1 | Output | AXI4-Lite write address ready signal |
| pl_vcu_wdata_axi_lite_apb | 32 | Input | AXI4-Lite write data channel |
| pl_vcu_wstrb_axi_lite_apb | 4 | Input | AXI4-Lite write strobe signal |
| pl_vcu_wvalid_axi_lite_apb | 1 | Input | AXI4-Lite write data valid signal |
| vcu_pl_wready_axi_lite_apb | 1 | Output | AXI4-Lite write ready signal |
| vcu_pl_bresp_axi_lite_apb | 2 | Output | AXI4-Lite write response channel |
| vcu_pl_bvalid_axi_lite_apb | 1 | Output | AXI4-Lite write response valid signal |
| pl_vcu_bready_axi_lite_apb | 1 | Input | AXI4-Lite write response ready signal |
| pl_vcu_araddr_axi_lite_apb | 20 | Input | AXI4-Lite read address channel |
| pl_vcu_arprot_axi_lite_apb | 3 | Input | AXI4-Lite read channel protection signal |
| pl_vcu_arvalid_axi_lite_apb | 1 | Input | AXI4-Lite read address valid signal |
| vcu_pl_arready_axi_lite_apb | 1 | Output | AXI4-Lite read address ready signal |
| vcu_pl_rdata_axi_lite_apb | 32 | Output | AXI4-Lite read data bus |
| vcu_pl_rresp_axi_lite_apb | 2 | Output | AXI4-Lite read response signal |
| vcu_pl_rvalid_axi_lite_apb | 1 | Output | AXI4-Lite read data valid signal |
| pl_vcu_rready_axi_lite_apb | 1 | Input | AXI4-Lite read data ready signal |
| VCU Encoder Buffer Interface | |||
| Vcu_pl_enc_al_l2c_rvalid | 1 | Output | Read data valid |
| Pl_vcu_enc_al_l2c_rready | 1 | Input | Read data ready |
| Vcu_pl_enc_al_l2c_addr | 17 | Output | Address |
| Pl_vcu_enc_al_l2c_rdata | 320 | Input | Read data |
| Vcu_pl_enc_al_l2c_wvalid | 1 | Output | Write data valid |
| Vcu_pl_enc_al_l2c_wdata | 320 | Output | Write data |