|
Core
Specifics |
| Supported Device Family
1
|
AMD Zynq™
UltraScale+™ MPSoC EV Devices |
| Supported User Interfaces |
AXI4
|
| Resources |
See Performance and Resource Utilization
|
| Provided with Core
|
| Design Files |
RTL |
| Example Design |
Not Provided |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Constraints File (XDC) |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
Vivado Design Suite
|
| Synthesis |
Vivado Design Suite
|
| Support |
| Release Notes and Known
Issues |
Master Answer Record:
66763
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web page
|
- For a complete list of
supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of
the tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|