The following figure shows the top-level interfaces and detailed architecture of the encoder block.
Figure 1. Detailed Architecture of the Encoder Block
Note: The AXI4 master interface
from the MCU is multiplexed with the corresponding AXI-4 Master interface from the
Decoder. The multiplexer output is available at the embedded VCU.
- The encoder block includes the compression engines, control registers, an interrupt controller, and an optional encoder buffer with a memory controller. The encoder buffer is connected to UltraRAM or block RAM in the programmable logic and enabled using registers.
- The encoder block is controlled by a microcontroller unit (MCU) subsystem, including a 32-bit MCU with a 32 KB instruction cache, a 1 KB data cache, and a 32 KB local SRAM.
- A 32-bit AXI4-Lite slave interface is used by the APU to control the MCU for the configuration of encoder parameters, to start/stop processing, to get status and to get results.
- Two 128-bit AXI4 master interfaces are used to fetch video input data, load and store intermediate data, store compressed data back to memory.
- A 32-bit AXI4 master interface is used to fetch the MCU software and load/store additional MCU data.
The VCU control software can change encoding parameters and even change between H.264 and H.265 encoding dynamically; however, the available memory and bandwidth must be selected to support the worst case needed by the application. Use the VCU GUI to explore bandwidth requirements.