The following figure shows the block diagram of the decoder block.
Figure 1. Detailed Architecture of the Decoder Block
The decoder block includes the H.265/H.264 decompression engine, control registers, and an interrupt controller block. The decoder block is controlled by an MCU subsystem. A 32-bit AXI4-Lite slave interface is used by the system CPU to control the MCU to configure decoder parameters, start processing of video frames and to get status and results. Two 128-bit AXI4 master interfaces are used to fetch video input data and store video output data from/to the system memory. An AXI4 master interface is used to fetch the MCU software and performs load/store operation on additional MCU data.