Clocking - 2024.1 English

The Decoder (VDEC) and Encoder (VENC) blocks work independently as separate units without any dependency on each other. The following table describes the clock domains in VCU core.

Table 1. VCU Clock Domains
Domain	Max Freq (MHz)	Description
Core clock	712	Processing core, most of the logic and memories
MCU clock	444	Internal micro controllers
AXI Master Port clock	333	`m_axi_enc_aclk` `m_axi_dec_aclk` `enc_buffer_clk` `pl_vcu_axi_mcu_clk` AXI master port for memory access, 128-bit, typically connected to PS AFI-FM (HP) port or to a soft memory controller in the PL.
AXI4-Lite slave port clock	167	`s_axi_lite_aclk`, AXI4-Lite slave port (32-bit) for register programming

Note: All AXI clocks are supplied with clocks from external PL sources. These clocks are asynchronous to core encoder, decoder, and MCU clocks. The VENC and VDEC cores are designed to handle asynchronous clocking in the AXI ports. The m_axi_mcu_aclk is asynchronous to all clocks used in VCU.

The following figure shows the clock generation options inside VCU block.

Note: The following blocks work on a single clock domain.

pll_ref_clk is sourced externally to the device, typically by a programmable clock integrated circuit.
Video encoder and decoder blocks work under the VENC_core_clk domain generated by the VCU PLL.
MCU for encoder and decoder work under the VENC_MCU_clk domain generated by the VCU PLL.
m_axi_enc_aclk is the AXI clock input from the PL for the 128-bit AXI master interfaces for the encoder.
m_axi_dec_aclk is the AXI clock input from the PL for the 128-bit AXI master interfaces for the decoder.
s_axi_lite_aclk is the AXI4-Lite clock from the PL.
m_axi_mcu_aclk is the MCU AXI master clock from the PL.
Figure 1. Clock Generation Options

The following clock frequency requirements must be met while providing clocks from PL:

The AXI clock for encoder and decoder interface is limited to 333 MHz.
The following ratio requirements need to be met:
- s_axi_lite_aclk ≤ 2 × m_axi_enc_aclk
- s_axi_lite_aclk ≤ 2 × m_axi_dec_aclk
Refer to Microcontroller Unit Overview for more information on the MCU.

The VENC_core_clk is generated based on the VCU PLL.

The VENC_MCU_clk is generated based on the VCU PLL.

The VDEC_core_clk is generated based on the VCU PLL.

The VDEC_MCU_clk is generated based on the VCU PLL.

Clocking - 2024.1 English - PG252

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)