XDC Constraints for SLR crossing at the SI side of SmartConnect. - 1.0 English

SmartConnect (PG247)

Document ID
PG247
Release Date
2022-10-19
Version
1.0 English

The example below is for interface s00, but can be applied to any s<nn> interface that crosses SLRs.

# SLR of Endpoint Master IP

create_pblock pblock_axi_master_on_si

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_ar_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_aw_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_b_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_r_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_w_node/inst/inst_si_handler]] -quiet

resize_pblock [get_pblocks pblock_axi_master_on_si] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9} # clock region defining SLR depends on device part

 

# SLR of SmartConnect core Switchboard

create_pblock pblock_smartconnect_switchboard

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_b_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_r_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_w_node/inst/inst_mi_handler]] -quiet

resize_pblock [get_pblocks pblock_smartconnect_switchboard] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4} # clock region defining SLR depends on device part