Slave Interface I/O Signals - Slave Interface I/O Signals - 1.0 English - PG247

SmartConnect LogiCORE IP Product Guide (PG247)
Document_ID
PG247
Release_Date
2026-06-24
Version
1.0 English

The following table lists the Slave Interface signals for the AXI SmartConnect core. In the Signal Name column, nn represents a two-digit sequence number (with leading zero) with range 00 ≤ nn ≤ N-1, where N refers to the total number of configured Slave Interfaces, which is the number of master devices connected to the AXI SmartConnect core. Each row in the table therefore defines N interface signals. When a range of values is specified in the Width column, the signal width is determined by the tools based on system connectivity.

Table 1. AXI SmartConnect Core Slave I/O Signals
Signal Name I/O Default Width Description (Range)
snn_axi_awid I AXI3, AXI4: 0

AXI4-Lite: d/c

 [1–32] Write Address Channel Transaction ID.
snn_axi_awaddr I REQ [2–64] Write Address Channel Address.
snn_axi_awlen I AXI3, AXI4: 0

AXI4-Lite: d/c

 AXI4: 8

AXI3: 4

 Write Address Channel Burst Length (0–255).
snn_axi_awsize I AXI3, AXI4: See Description

AXI4-Lite: d/c

 3 Write Address Channel Transfer Size

code (0–7). When not connected, the data transfer size for all transactions is assumed to be the full interface data width.
snn_axi_awburst I AXI3, AXI4: 0b01

AXI4-Lite: d/c

 2 Write Address Channel Burst Type code (0–2). When not connected, all transactions are assumed to be increment burst type (INCR).
snn_axi_awlock I

AXI3, AXI4: 0

AXI4-Lite: d/c

 AXI4: 1

AXI3: 2

 Write Address Channel Atomic Access Type:

0= No locked access

1= Exclusive Access

2, 3= Not supported
snn_axi_awcache I AXI3, AXI4: 0

AXI4-Lite: d/c

 4 Write Address Channel Cache Characteristics.
snn_axi_awprot I 0b000 1 3 Write Address Channel Protection Bits.
snn_axi_awqos 2 I AXI4: 0

AXI4-Lite: d/c

 4 AXI4 Write Address Channel Quality of Service.
snn_axi_awuser I AXI3, AXI4: 0

AXI4-Lite: d/c

 [1–512] 3 User-defined AW Channel signals.
snn_axi_awvalid I REQ 1 Write Address Channel Valid.
snn_axi_awready O 1 Write Address Channel Ready.
snn_axi_wid I AXI3: 0

AXI4, AXI4-Lite: d/c

 [1–32] Write Data Channel Transaction ID for AXI3 masters.
snn_axi_wdata I REQ [32, 64, 128, 256, 512, 1024] Write Data Channel Data.
snn_axi_wstrb I all ones [32, 64, 128, 256, 512, 1024] / 8 Write Data Channel Byte Strobes.
snn_axi_wlast I AXI3, AXI4: 0

AXI4-Lite: d/c

 1 Write Data Channel Last Data Beat.
snn_axi_wuser I AXI3, AXI4: 0

AXI4-Lite: d/c

 [1–512] 3 User-defined W Channel signals; must be an integer number of bits per byte of wdata .
snn_axi_wvalid I REQ 1 Write Data Channel Valid.
snn_axi_wready O 1 Write Data Channel Ready.
snn_axi_bid O [1–32] Write Response Channel Transaction ID.
snn_axi_bresp O 2 Write Response Channel Response Code (0–3).
snn_axi_buser O 1-512 3 User-defined B Channel signals.
snn_axi_bvalid O 1 Write Response Channel Valid.
snn_axi_bready I REQ 1 Write Response Channel Ready.
snn_axi_arid I AXI3, AXI4: 0

AXI4-Lite: d/c

 [1–32] Read Address Channel Transaction ID.
snn_axi_araddr I REQ [2–64] Read Address Channel Address.
snn_axi_arlen I AXI3, AXI4: 0

AXI4-Lite: d/c

 AXI4: 8

AXI3: 4

 Read Address Channel Burst Length code (0–255).
snn_axi_arsize I AXI3, AXI4: See Description

AXI4-Lite: d/c

 3 Read Address Channel Transfer Size code (0-7). When not connected, the data transfer size for all transactions is assumed to be the full interface data width.
snn_axi_arburst I AXI3, AXI4: 2b01

AXI4-Lite: d/c

 2 Read Address Channel Burst Type code (0-2). When not connected, all transactions are assumed to be increment burst type (INCR).
snn_axi_arlock I AXI3, AXI4: 0

AXI4-Lite: d/c

 AXI4: 1

AXI3: 2

 Read Address Channel Atomic Access Type:

0 = No locked access

1 = Exclusive Access

2, 3 = Not supported
snn_axi_arcache I AXI3, AXI4: 0

AXI4-Lite: d/c

 4 Read Address Channel Cache Characteristics.
snn_axi_arprot I 0b000 1 3 Read Address Channel Protection Bits.
snn_axi_arqos 2 I AXI4: 0

AXI4-Lite: d/c

 4 AXI4 Read Address Channel Quality of Service.
snn_axi_aruser I AXI3, AXI4: 0

AXI4-Lite: d/c

 [1–512] 3 User-defined AR Channel signals.
snn_axi_arvalid I REQ 1 Read Address Channel Valid.
snn_axi_arready O 1 Read Address Channel Ready.
snn_axi_rid O [1–32] Read Data Channel Transaction ID.
snn_axi_rdata O [32, 64, 128, 256, 512, 1024] Read Data Channel Data.
snn_axi_rresp O 2 Read Data Channel Response Code (0–3).
snn_axi_rlast O 1 Read Data Channel Last Data Beat.
snn_axi_ruser O [1–512] 3 User-defined R Channel signals.
snn_axi_rvalid O 1 Read Data Channel Valid.
snn_axi_rready I REQ 1 Read Data Channel Ready.
  1. AXI protocol requires master devices to drive their awprot/arprot outputs. If the awprot/arprot signals are left undriven, it defaults to all zeros and the transaction is interpreted as secure.
  2. Although the awqos/arqos signals are defined only by the AXI4 protocol specification, this SmartConnect IP core also propagates QoS signals for any SI configured as AXI3.
  3. When connected to another SmartConnect instance (cascaded), the width of the user signal for each channel is 1024, and the signal carries proprietary SmartConnect control fields in addition to the user-defined signal value.