SmartConnect offers various pipelining and register slice options that can be user configured to tune system trade-offs between area, latency, and timing. Enabling pipelines and register slices can improve timing, but can also introduce latency and consume significant area, especially with large data widths.
Register slices options are available on each SI (see 'Snn_Entry' in Advanced Properties) and MI (see 'Mnn_Exit' Advanced Properties) interface of the SmartConnect to isolate its timing from an attached AXI master/slave IP.
Around the buffer and switchboard blocks inside the SmartConnect, there are additional SI (see 'Snn_Buffer' in Advanced Properties) and MI (see 'Mnn_Buffer' in Advanced Properties) pipelining options which introduce ranks of FFs that can improve timing internal to the SmartConnect. Options for SLR pipeline ranks are suitable for SLR crossings and general purpose pipelining within an SLR.