Master Interface I/O Signals - Master Interface I/O Signals - 1.0 English - PG247

SmartConnect LogiCORE IP Product Guide (PG247)
Document_ID
PG247
Release_Date
2026-06-24
Version
1.0 English
The following table lists the Master Interface signals for the AXI SmartConnect core. In the Signal Name column, nn represents a two-digit sequence number (with leading zero) with range 00 ≤ nn ≤ N–1, where N refers to the total number of configured Master Interfaces, which is the number of slave devices connected to the AXI SmartConnect core. Each row in the table therefore defines N interface signals. When a range of values is specified in the Width column, the signal width is determined by the tools based on system connectivity.
Table 1. AXI SmartConnect Core Master I/O Signals
Signal Name I/O Default Width Description (Range)
mnn_axi_awid O   [1–32] Write Address Channel Transaction ID.
mnn_axi_awaddr O   [2–64] Write Address Channel Address.
mnn_axi_awlen O   AXI4: 8

AXI3: 4

 Write Address Channel Burst Length code. (0–255).
mnn_axi_awsize O   3 Write Address Channel Transfer Size code (0–7).
mnn_axi_awburst O   2 Write Address Channel Burst Type. This signal (if enabled) is always driven to 2b01 (INCR burst type).
mnn_axi_awlock O   AXI4: 1

AXI3: 2

 Write Address Channel Atomic Access Type (0, 1).
mnn_axi_awcache O   4 Write Address Channel Cache Characteristics.
mnn_axi_awprot O   3 Write Address Channel Protection Bits.
mnn_axi_awqos 1 O   4 Write Address Channel Quality of Service.
mnn_axi_awuser O   [1–512] 2 User-defined AW Channel signals.
mnn_axi_awvalid O   1 Write Address Channel Valid.
mnn_axi_awready I REQ 1 Write Address Channel Ready.
mnn_axi_wid O   [1–32] Write Data Channel Transaction ID for AXI3 slaves.
mnn_axi_wdata O   [32, 64, 128, 256, 512, 1024] Write Data Channel Data.
mnn_axi_wstrb O   [32, 64, 128, 256, 512, 1024] / 8 Write Data Channel Data Byte Strobes.
mnn_axi_wlast O   1 Write Data Channel Last Data Beat.
mnn_axi_wuser O   [1–512] 2 User-defined W Channel signals.
mnn_axi_wvalid O   1 Write Data Channel Valid.
mnn_axi_wready I REQ 1 Write Data Channel Ready.
mnn_axi_bid I AXI3, AXI4: REQ

AXI4-Lite: d/c

 [1–32] Write Response Channel Transaction ID.
mnn_axi_bresp I 0b00 2 Write Response Channel Response Code (0–3).
mnn_axi_buser I AXI3, AXI4: 0

AXI4-Lite: d/c

 [1–512] 2 User-defined B Channel signals.
mnn_axi_bvalid I REQ 1 Write Response Channel Valid.
mnn_axi_bready O   1 Write Response Channel Ready.
mnn_axi_arid O   [1–32] Read Address Channel Transaction ID.
mnn_axi_araddr O   [2–64] Read Address Channel Address.
mnn_axi_arlen O   AXI4: 8

AXI3: 4

 Read Address Channel Burst Length code (0–255).
mnn_axi_arsize O   3 Read Address Channel Transfer Size code (0–7).
mnn_axi_arburst O   2 Read Address Channel Burst Type. This signal (if enabled) is always driven to 2b01 (INCR burst type).
mnn_axi_arlock O   AXI4: 1

AXI3: 2

 Read Address Channel Atomic Access Type (0,1).
mnn_axi_arcache O   4 Read Address Channel Cache Characteristics.
mnn_axi_arprot O   3 Read Address Channel Protection Bits.
mnn_axi_arqos 1 O   4 AXI4 Read Address Channel Quality of Service.
mnn_axi_aruser O   [1–512] 2 User-defined AR Channel signals.
mnn_axi_arvalid O   1 Read Address Channel Valid.
mnn_axi_arready I REQ 1 Read Address Channel Ready.
mnn_axi_rid I AXI3, AXI4: REQ

AXI4-Lite: d/c

 [1–32] Read Data Channel Transaction ID.
mnn_axi_rdata I REQ [32, 64, 128, 256, 512, 1024] Read Data Channel Data.
mnn_axi_rresp I 0b00 2 Read Data Channel Response Code (0–3).
mnn_axi_rlast I

AXI3, AXI4: REQ

AXI4-Lite: d/c

 1 Read Data Channel Last Data Beat.
mnn_axi_ruser I AXI3, AXI4: 0

AXI4-Lite: d/c

 [1–512] 2 User-defined R Channel signals.
mnn_axi_rvalid I REQ 1 Read Data Channel Valid.
mnn_axi_rready O   1 Read Data Channel Ready.
  1. Although the QOS signals are defined only by the AXI4 protocol specification, the SmartConnect IP core also propagates QOS signals for any MI configured as AXI3.
  2. When connected to another SmartConnect instance (cascaded), the width of the user signal for each channel is 1024, and the signal carries proprietary SmartConnect control fields in addition to the user-defined signal value.