Introduction - 1.0 English

SmartConnect (PG247)

Document ID
PG247
Release Date
2022-10-19
Version
1.0 English

The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

Note:   The AXI SmartConnect core is intended for memory-mapped transfers only. For AXI4-Stream transfers, see the LogiCORE IP AXI4-Stream InterConnect Product Guide (PG085) [Ref 1].

The AXI SmartConnect is a Hierarchical IP block that is added to a Vivado® IP integrator block design in the Vivado Design Suite.

Note:   AXI SmartConnect is not available for direct (standalone) instantiation from the Xilinx IP catalog for use directly in a RTL design.

AXI SmartConnect is a drop-in replacement for the AXI Interconnect v2 core. SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention.

LogiCORE IP Facts Table

Core Specifics

Supported Device Family(1)

Versal® ACAP

UltraScale+™ devices

UltraScale™ devices
7 Series FPGAs

Supported User Interfaces

AXI4, AXI4-Lite, AXI3

Resources

Performance and Resource Utilization web page

Provided with Core

Design Files

Verilog

Example Design

Not Provided

Test Bench

Not Provided

Constraints File

Xilinx Design Constraints (XDC)

Simulation Model

Not Provided

Supported
S/W Driver

N/A

Tested Design Flows(2)

Design Entry

Vivado® Design Suite

Simulation

For supported simulators, see the
Xilinx Design Tools: Release Notes Guide

Synthesis

Vivado Synthesis

Support

Release Notes and Known Issues

Master Answer Record: 66780

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

 Xilinx Support web page

Notes:

1.For a complete list of supported devices, see the Vivado IP catalog.

2.For the supported versions of third-party tools, see the
Xilinx Design Tools: Release Notes Guide.