Global Port Signals - Global Port Signals - 1.0 English - PG247

SmartConnect LogiCORE IP Product Guide (PG247)

Document_ID
PG247
Release_Date
2026-06-24
Version
1.0 English
Table 1. AXI SmartConnect Core Global Port Signals
Port Signal Name I/O Default Width Description (Range)
aclk I REQ 1 SmartConnect clock input.
aclk1…aclkn I REQ when enabled 1 Clock inputs for additional interface clock domains.
aclken, aclken1…aclkenn I 1 1 Clock enable input associated with each clock domain.
aresetn I REQ 1 SmartConnect Reset (active-Low).