Feature Comparison - Feature Comparison - 1.0 English - PG247

This section highlights the feature differences between AXI SmartConnect v1.0 and AXI Interconnect v2.1.

• The individual conversion and storage modules used in SmartConnect are not available as stand-alone IP. Visibility of internal logic blocks inside SmartConnect is not supported.
• SmartConnect provides parallel destination-side arbitration on all AXI channels (Multiple-Address Multiple-Data (MAMD) topology instead of Single-Address Multiple-Data (SAMD)).
• SmartConnect supports back-to-back arbitration and propagation on AW and AR channels (supporting high-bandwidth for single-beat transactions).
• SmartConnect supports multi-threaded traffic, if enabled, through all data width conversions, protocol conversions (except AXI4-Lite), and transaction splitting.
• SmartConnect propagates User-defined signals on all channels through all data width conversions, protocol conversions (except AXI4-Lite), and transaction splitting.
• By default, SmartConnect does not propagate ID signals to a connected endpoint slave. SmartConnect still supports multi-threaded traffic across the interconnect topology, allowing endpoint masters to access multiple slaves concurrently and receive responses out-of-order from among those slaves. SmartConnect optionally supports "MI multi-threading", where ID signals are issued to endpoint slaves to allow them to respond out-of-order, provided they have that capability. Refer to MI Multi-threading in Non-GUI Advanced Properties.
• One clock input per clock domain instead of one clock input per SI/MI interface.
• One reset input for the whole IP instead of one reset per SI/MI interface.
• SmartConnect performs address decode and error detection only at the endpoint SI interface, not repeated by each cascaded SmartConnect instance.
• SmartConnect does not support propagation of WRAP type bursts; WRAP bursts are automatically converted to INCR type bursts.
• FIXED burst type transactions are no longer supported.
• SmartConnect does not support propagation of narrow bursts (awsize/arsize less than the full interface data width); all bursts are fully packed, regardless of the “modifiable” bit in awcache/arcache.
• The awregion/arregion signals are no longer generated on the MI.
• SmartConnect performs deadlock avoidance checking only at the endpoint SI interface, not repeated by each cascaded SmartConnect instance.
• At this time, SmartConnect provides an area-optimized Low-Area Mode only when all MIs are connected to 32-bit AXI4-Lite endpoints and all SI (if more than one) are in the same clock domain. For any other configurations where an area-optimized mode is preferred, continue to use axi_interconnect_v2_1 in area strategy mode. Refer to Reduced Area Mode in Non-GUI Advanced Properties.
• The AXI Interconnect v2 core supports a maximum of 16 address segments per MI. SmartConnect supports a total of 256 address segments across all MI.