Constraining the Core - Constraining the Core - 1.0 English

In general, the only constraints required when deploying the SmartConnect core is the specification of a clock period constraint for each of the clock signals connected to all aclk inputs of the core. Placement constraints might also be needed when the SmartConnect is required to span across super logic regions (SLRs).

Required Constraints

When the SmartConnect is configured to use the SLR crossing pipelines, and the given SI or MI interface will cross an SLR boundary, placement constraints can improve timing and placement of these pipelining FFs.

XDC Constraints for SLR crossing at the SI side of SmartConnect.

The following example is for interface s00, but can be applied to any s<nn> interface that crosses SLRs.

# SLR of Endpoint Master IP

create_pblock pblock_axi_master_on_si

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_ar_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_aw_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_b_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_r_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_master_on_si] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_w_node/inst/inst_si_handler]] -quiet

resize_pblock [get_pblocks pblock_axi_master_on_si] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9} # clock region defining SLR depends on device part

 

# SLR of SmartConnect core Switchboard

create_pblock pblock_smartconnect_switchboard

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_b_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_r_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/s00_nodes/s00_w_node/inst/inst_mi_handler]] -quiet

resize_pblock [get_pblocks pblock_smartconnect_switchboard] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4} # clock region defining SLR depends on device part

XDC Constraints for SLR crossing at the MI side of SmartConnect.

The following example is for interface m00 but can be applied to any m<nn> interface that crosses SLRs.

# SLR of SmartConnect core Switchboard

create_pblock pblock_smartconnect_switchboard

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_ar_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_aw_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_b_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_r_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_smartconnect_switchboard] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_w_node/inst/inst_si_handler]] -quiet

resize_pblock [get_pblocks pblock_smartconnect_switchboard] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9} # clock region defining SLR depends on device part

 

# SLR of Endpoint Slave IP

create_pblock pblock_axi_slave_on_mi

add_cells_to_pblock [get_pblocks pblock_axi_slave_on_mi] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_slave_on_mi] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_slave_on_mi] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_b_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_slave_on_mi] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_r_node/inst/inst_si_handler]] -quiet

add_cells_to_pblock [get_pblocks pblock_axi_slave_on_mi] [get_cells [list <netlist_path_SC_component>/inst/m00_nodes/m00_w_node/inst/inst_mi_handler]] -quiet

resize_pblock [get_pblocks pblock_axi_slave_on_mi] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4} # clock region defining SLR depends on device part