AXI SmartConnect Core Limitations - AXI SmartConnect Core Limitations - 1.0 English - PG247

The following limitations apply to the AXI SmartConnect core:

• SmartConnect unconditionally packs all multi-beat bursts to fill the interface data-width.

  SmartConnect SI interfaces accept narrow bursts, in which the arsize or awsize signal indicates data units which are smaller than the interface data-width. In Performance mode, such bursts are always propagated through the SmartConnect core and its MI interfaces fully packed. The modifiable bit of the AXI arcache or awcache signal does not prevent packing.

  When a single-beat transaction (arlen = 0 or awlen = 0) is received and the arsize/awsize signal indicate a data unit smaller than the data-width of the targeted MI, the narrow size of the single-beat transaction is preserved and propagated to the MI, so that the range of address locations originally specified by the master are not exceeded.

• SmartConnect converts all WRAP type bursts into INCR type. SmartConnect SI interfaces accept all protocol-compliant WRAP bursts, beginning at any target address. But such bursts are converted to a single INCR burst or a series of single-beat transactions. This can increase response latency of unaligned read wrap bursts.
• SmartConnect does not support FIXED type bursts. Any FIXED burst transaction received at the SmartConnect SI is blocked and a DECERR response is returned to the master.
• By default, SmartConnect does not propagate ID values on the MI to the connected slave. IDs received at an SI interface are used internally by SmartConnect for reordering and response routing. These are stored internally and restored during response transfers.
  • AXI ID signals cannot be used in the system to identify the master originating an AXI transaction. Instead, AMD recommends using the aruser and awuser signals to convey master identification information, as needed.
• The AXI SmartConnect core does not support discontinued AXI3 features:

  Atomic locked transactions

  This feature was retracted by the AXI4 protocol. A locked transaction is changed to a non-locked transaction and propagated by the MI.

  Write interleaving

  This feature was retracted by the AXI4 protocol. AXI3 master devices must be configured as if connected to a slave with a Write interleaving depth of one.

• By default, all arbitration on all AXI channels is round-robin.
• AXI4 Quality of Service (arqos and awqos ) signals do not influence arbitration priority. QoS signals are propagated from SI to MI.
• SmartConnect neither propagates nor generates the AXI4 arregion or awregion signal.
• SmartConnect does not support independent reset domains. If any master or slave device connected to SmartConnect is reset, then all connected devices must be reset concurrently.
• SmartConnect does not propagate the AXI Low power interface (C-channel) signals.
• SmartConnect does not time out if the destination of any AXI channel transfer stalls indefinitely. All connected AXI slaves must respond to all received transactions, as required by AXI protocol.
• SmartConnect provides no address remapping.
• SmartConnect does not include conversion or bridging to non-AXI protocols, such as APB.