AXI Protocol Violations - 1.0 English

SmartConnect (PG247)

Document ID
PG247
Release Date
2022-10-19
Version
1.0 English

When designing with custom or non-production IP, it is common to encounter system malfunctions caused by AXI protocol violations. Xilinx AXI IP cores, including SmartConnect, do not contain any logic to guard against AXI protocol violations incurred by IP cores to which they are connected.

One of the most common symptoms of an AXI protocol violation in a system is an apparent lock-up of a connected core. The SmartConnect core is especially vulnerable to protocol violations incurred by connected IP cores. When such a lock-up condition occurs, it often appears that an AXI channel transfer (valid/ready handshake) completes on one interface of the SmartConnect, but the resultant transfer is never issued on the expected output interface. Other possible symptoms include output transfers that appear to violate AXI transaction ordering rules.

 

RECOMMENDED:   Xilinx strongly recommends that you use the available AXI Protocol Checker IP core to test for AXI protocol compliance before deploying any custom IP or IP with custom modifications.