The AXI4-Stream, memory mapped
AXI4, and AXI4-Lite interfaces must be synchronous to the core
clock signal ap_clk. All AXI4-Stream, memory
mapped AXI4 interface input signals and AXI4-Lite control
interface input signals are sampled on the rising edge of ap_clk. All AXI4-Stream output signal changes occur after the rising
edge of ap_clk.