Top-Level Registers - 5.3 English - PG243

Video Mixer LogiCORE IP Product Guide (PG243)

Document ID: PG243
Release Date: 2025-05-29
Version: 5.3 English

The following table provides a detailed description of all the registers that apply globally to the IP.

Table 1. Top-Level Registers
Address (hex) BASEADDR+	Register Name	Access Type	Register Description
0x0000	Control	R/W	Bit[0] = ap_start (R/W/COH) ¹ Bit[1] = ap_done (R/COR)¹ Bit[2] = ap_idle (R) Bit[3] = ap_ready (R) Bit[5] = Flush pending AXI transactions (R/W)² Bit[6] = Flush done (R) Bit[7] = auto_restart (R/W) Others = reserved
0x0004	Global Interrupt Enable	R/W	Bit[0] = Global interrupt enable Others = Reserved
0x0008	IP Interrupt Enable		Bit[0] = ap_done Bit[1] = ap_ready Others = reserved
0x000C	IP Interrupt Status Register	R/TOW¹	Bit[0] = ap_done Bit[1] = ap_ready Others = Reserved
0x0010	Width	R/W	Active width of background.
0x0018	Height	R/W	Active height of background.
0x0028	Background R or Y	R/W	Red or Y value of background color
0x0030	Background U or G	R/W	Green or U value of background color
0x0038	Background V or B	R/W	Blue or V value of background color
0x0040	Layer enable	R/W	Bit[0] = Master layer is enabled/disabled Bit[1] = Overlay Layer 1 is enabled/disabled … Bit[16] = Overlay Layer 16 is enabled/disabled Bit[23] = Logo layer is enabled/disabled
TOW = Toggle on Write, COH = Clear on Handshake, COR = Clear on Read. BIT[5] and BIT[6] are applicable only for memory based layers. Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in section S_AXILITE Control Register Map of Vitis High-Level Synthesis User Guide (UG1399). These registers’ definitions might have some additional bits; however, in the current IP, you can access only the bits mentioned in the preceding table. Therefore, only these bits need to be considered while accessing the above registers.