The Video Mixer supports
bi-directional data throttling between its AXI4-Stream slave and master interfaces. If the slave side
data source is not providing valid data samples (s_axis_video_tvalid is not asserted), the core cannot
produce valid output samples after its internal buffers are depleted.
Similarly, if the master side interface is not ready to accept valid data
samples (m_axis_video_tready is not
asserted) the core cannot accept valid input samples after its buffers
become full.
If the master interface is able to provide valid samples
(s_axis_video_tvalid is High) and the slave
interface is ready to accept valid samples
(m_axis_video_tready is High), typically the core
can process and produce one, two, four, and eight pixels specified by
Samples Per Clock in the
AMD Vivado™
Integrated Design Environment (IDE) per
ap_clk cycle.
However, at the end of each scan
line and frame the core flushes internal pipelines for several
clock cycles, during which the s_axis_video_tready is deasserted signaling
that the core is not ready to process samples.
When the Video Mixer is processing timed streaming video (which is typical for most video sources), the flushing periods coincide with the blanking periods and therefore do not reduce the throughput of the system.
When operating on a streaming video source (that is, not frame buffered data), the Video Mixer must operate minimally at the burst data rate. For example, 148.5 MHz for a 1080p60 video source for a one sample per clock configuration of the IP. For a 4K 60 fps video source, the core must operate at 297 MHz for a two sample per clock configuration, or 148.5 MHz for a four sample per clock configuration on slower devices such as AMD Artix™ 7.