Synthesizable Example Design - 5.3 English

The difference between the Synthesizable design and the Simulation example design is the use of a microprocessor instead of the AXI VIP core as AXI4 master. In addition, the synthesizable design uses the MIG IP core for DDR memory access. The locked port of AXI4-Stream to Video Out is connected to axi_gpio_lock core and the processor polls the corresponding register for a sign that the test passed. The following figure shows a synthesizable example design.

Figure 1. Synthesizable Example Block Design

The synthesizable example design requires both Vivado and AMD Vitis™ tools.

The first step is to run synthesis, implementation, and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware. In the window, select Include bitstream , select an export directory and click OK to create an XSA project.

Figure 2. Export Hardware

The remaining work is performed in the AMD Vitis tool. The Video Mixer example design file can be found in the following Vitis directory:

(<install_directory>/<release>/data/embeddedsw/XilinxProcessorIPLib/drivers/v_mix_v6_1/examples/

The example application design source files (contained within examples folder) are tightly coupled with the v_mix example design available in Vivado IP catalog.

Perform the following steps to get the .elf file from the Vitis application.

Open the Vitis application. Set workspace path by selecting Get Started > Set Workspace.
Create the platform component by selecting Embedded Development > Create Platform Component.
Enter the Component name and Component location in the pop-up window and click Next.
Select the required XSA.
Select the Operating System, Processor, and Compiler.
Review the summary and click Finish.
Once the platform component is created, switch to the welcome panel, and select the Create Empty Embedded Application option in Embedded Development > Create Platform Component.
Choose the Component name and Component location in the pop-up window. Select Next.
Select the required Platform in the hardware tab and click Next.
Choose the domain from the available domains.
Add source files or skip for now, review the summary, and click Finish.
If skipped in the previous step, import the source files into the app component by right clicking on sources and selecting Import > Files.
Import the required files.
Build the project by selecting Flow > Build. When prompted for Platform build, select Yes.
Once the build is complete, check the Output folder for the elf file.

The vmix_example.tcl automates the process of generating the downloadable bit and elf files from the provided example xsa file.

To run the provided Tcl script:

Copy the exported example design xsa file in the examples directory of the driver
Launch the Xilinx Software Command-Line Tool (xsct) terminal
cd into the examples directory
Source the tcl file xsct :
%>source vmix_example.tcl
Execute the script:
xsct%>vmix_example xsa_file_name.xsa

The Tcl script performs the following:

Create workspace
Create HW project
Create BSP
Create Application Project
Build BSP and Application Project

After the process is complete, the required files are available in:

bit file ->v_mix_0_ex/ folder

elf file -> v_mix_0_ex/sdk/xv_mix_example_1{Debug/Release} folder

Next, perform the following steps to run the software application:

Important: To do so, make sure that the hardware is powered on and a Digilent Cable or an USB Platform Cable is connected to the host PC. Also, ensure that a USB cable is connected to the UART port of the board.

Launch the Vitis application.
Set workspace to vmix_example.sdk folder in prompted window. The SDK project opens automatically (if a welcome page shows up, close that page).
Download the bitstream into the FPGA by selecting Xilinx Tools > Program FPGA. The Program FPGA dialog box opens.
Ensure that the Bitstream field shows the bitstream file generated by Tcl script, and then click Program .
Note: The DONE LED on the board turns green if the programming is successful.
A terminal program (Hyper Terminal or PuTTY) is needed for UART communication. Open the program, choose appropriate port, set baud rate to 115,200, and establish Serial port connection.
Select and right-click the application vmix_example_design in Project_Explorer panel.
Select Run As > Launch on Hardware (GDB).
Select Binaries and Qualifier in window and click OK.

The example design test result are shown in terminal program.

Synthesizable Example Design - 5.3 English - PG243

Video Mixer LogiCORE IP Product Guide (PG243)