Prerequisites - 6.0 English - PG243

If optional layers are enabled and configured as "Memory", there are certain requirements that must be taken care of while programming the core.

1. The core itself does not have a data realignment engine and therefore the application software must align the layer memory addresses before writing to the registers. The alignment requirement is specified below, and makes sure that the start address is aligned with the width of the memory interface.

   2 × Pixels per Clock × 4 Bytes

2. The Stride value (in bytes) must be aligned as above to make sure that every row of pixels starts at an aligned memory location. Use the following equation to compute the stride from the width (in pixels) in raster-scan order:

   Stride in Bytes ≥ (Width × Bytes per Pixel)

   The bytes per pixel value varies per video in memory format, and is described in Memory Mapped AXI4 Interface.

   Use the following equation to compute the stride from the width (in pixels) in tile-scan order for a tile size of n × 4 (where n = 32 or 64):

   Stride in Bytes ≥ (((Width + (n-1)) & ~(n-1)) * 4 * bit-depth) / 8
   Note: Due to a current limitation of the IP core when configured for samples per clock=8, the minimum stride required for tiled video format with bit-depth=10 needs to be calculated using n=64 in the above formula. This calculation applies to both 32x4 and 64x4 tiles.

   Padding bytes is sometimes necessary (hence, the ≥ in the equation) to make sure that every row of pixels starts at an address that is aligned with the size of the data on the memory mapped interface as described in Layer Stride (0x0#20) Register.

3. Layer Window Start Horizontal Position and Width must be a multiple of Pixels per Clock as selected in the Vivado Integrated Design Environment (IDE) for this core.
4. In Tile video format, the Width value must be a multiple of 4 and Pixels per Clock. The Height value must be a multiple of 8.