In case the layer is a memory layer, the Layer Plane 1 Buffer register specifies the frame buffer address of plane 1. For the semi-planar formats (Y_UV8, Y_UV8_420, Y_UV10, and Y_UV10_420), the chroma buffer is specified by the Layer Plane 2 Buffer register. For the planar formats (Y_U_V8, Y_U_V10, and Y_U_V12), the U chroma buffer is specified by the Layer Plane 2 Buffer register and V chroma buffer is specified by the Layer Plane 3 Buffer register. The addresses must be aligned to the data size of the memory mapped AXI4 interface. For the Video Mixer, the data size of the memory mapped AXI4 interface is 64 × Samples per Clock bits, that is, 64, 128, 256, and 512 bits for 1, 2, 4, and 8 samples per clock, respectively. These registers are not applicable when the layer is a streaming layer.