| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
AMD Versal™ Adaptive SoC, AMD UltraScale+™ Families, AMD UltraScale™ Architecture, AMD Zynq™ 7000 SoC, 7 series FPGAs |
| Supported User Interfaces | AXI4-Lite Master, AXI4-Lite, AXI4-Stream 2 |
| Resources | Performance and Resource Use web page |
| Provided with Core | |
| Design Files | Not Provided |
| Example Design | Yes |
| Test Bench | Not Provided |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | Encrypted RTL |
| Supported S/W Driver 2 | Standalone DRM/KMS |
| Tested Design Flows 3 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: AR 66753 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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