The Versal Adaptive SoC Transceiver Wizard
generates txoutclk and rxoutclk at the correct frequency to use as core_clk. However, the output phase of these clocks varies from reset to
reset. This means that for JESD204 interfaces the Versal Adaptive SoC Transceiver outclock
ports might only be used to drive core_clk when Subclass
0 is used and deterministic latency is not required. For systems that require
deterministic latency and therefore use Subclass 1 or Subclass 2, the Versal Adaptive SoC Transceiver outclocks should not be used.
The rest of this section details the valid clocking architecture options.