Using Multiple JESD204C Cores to Connect to One or More ADCs Across SLR Boundaries - Using Multiple JESD204C Cores to Connect to One or More ADCs Across SLR Boundaries - 4.3 English - PG242

In some cases, it might be necessary to connect multiple JESD204C cores to more than one ADC across SLR boundaries, while making sure that there is no latency between them. The following figure shows an example of Multiple RX cores in separate SLRs.

Some important points are listed here:

• The whole system is synchronous and as such all clocks should be generated from a common source.
• Each GT quad or GT Wizard subsystem requires its own refclk.
• All JESD204C RX cores share a single common core_clk:
  • Both separate refclk and core_clk and refclk as core_clk clocking schemes are supported. For more information, see Clocking.
  • However if refclk as core_clk is used then core_clk is generated from only one of the refclk.

• core_clk is used as the AXI4-Stream clock for both JESD204C RX AXI4-Stream data interfaces.
• To ensure successful capture of SYSREF by both JESD204C RX cores, a D type flip flop should be placed on the input SYSREF signal.
  • The output of this should then be fed into both JESD204C RX cores.
  • The T_su and T_hd requirements of this flip flop with respect to the core_clk must be met.
  • Should there be issues with closing timing for SYSREF over the SLR boundary, additional FFs are needed for the SLR crossing. This additional delay can be compensated for in the SYSREF delay settings between the cores.

The output of both JESD204C RX cores are aligned with no latency differences if the above recommendation are implemented correctly.

To confirm this:

• Monitor the AXI4-Stream rx_tvalid signals. They should both be asserted HIGH on the same core_clk cycle.
• Monitor the start of EMB signals (64b66b) or start of frame and multiframe signals (8b10b) on each JESD204C RX core. They should be identical.

There are two options to process the received data from each JESD204C RX core:

• The first option is to use the output data separately in their respective SLRs.
• The second option is shown in the previous image, an example of how you can combine the output data into one SLR using AXIS Register Slice IPs configured for SLR crossing.