Upgrading - 4.3 English - PG242

JESD204C v4.3 LogiCORE IP Product Guide (PG242)

Document ID: PG242
Release Date: 2025-12-03
Version: 4.3 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Unsupported Features
Licensing and Ordering
License Checkers
Product Specification
Standards
Performance
Port Descriptions
TX Core
RX Core
Register Space
Designing with the Core
General Design Guidelines
Use the Example Design
Know the Degree of Difficulty
Registering Signals
Recognize Timing Critical Signals
Use Supported Design Flows
Make Only Allowed Modifications
Recommended Design Experience
Subclass Mode
Subclass 0
Subclass 1
Subclass 2
Programming the Core
Clocking
Core Clock 64B66B Linecoding
Core Clock 8B10B Linecoding
Reference Clock
JESD204_PHY Outclocks for UltraScale+/UltraScale Devices
Versal Adaptive SoC Transceiver Outclocks
Versal Adaptive SoC GTM Transceiver Clocking
AXI4-Lite Interface Clock
DRP Clock for UltraScale+/UltraScale Devices
Separate Transceiver Reference and Core Clocks
Transceiver Reference Clock Used as Core Clock
Transceiver Reference Clock Used as Core Clock
Clocking Considerations
Resets
Data and Command Interfaces
SYSREF
SYSREF Timing
SYSREF Type
SYSREF Handling
SYSREF Delay
SYSREF Always
SYSREF Required
Capturing SYSREF
SYSREF on Initial Link Bring-Up with 8B10B Linecoding
SYSREF on Link Resynchronization with 8B10B Linecoding
SYSREF on Initial Link Bring-Up with 64B66B Linecoding
SYSREF on Link Resynchronization with 64B66B Linecoding
Subclass 2 Operation (8B10B Line Coding Only)
Number of Lanes per Link
Receive Latency
RX End to End Latency
8B10B Line Coding
ADC Timing
Core Timing
Calculating End to End Latency
Step 1: Determine How Many LMFC Periods are Required (N)
Step 2: Calculate the End to End Latency Using N
Example
64B66B Line Coding
ADC Timing
Core Timing
Calculating End to End Latency
Achieving Repeatable Latency
8B10B Line Coding
Procedure - Achieving Repeatable Latency
64B66B Line Coding
Procedure - Achieving Repeatable Latency
Receiver Elastic Buffer
Minimum Deterministic Latency Support
Error Signaling Using the SYNC~ Interface (8B10B only)
Link Reinitialization (8B10B only)
Transmit Latency
TX End to End Latency
8B10B Line Coding
Core Timing
DAC Timing
Calculating End to End Latency
Step 1: Determine How Many LMFC Periods are Required (N)
Step 2: Calculate the End to End Latency Using N
Example
Transmitter Phase Adjustment for Subclass 2
64B66B Line Coding
Core Timing
DAC Timing
Calculating End to End Latency
Design Flow Steps
Customizing and Generating the Core
Configuration Tab
GT Wizard Configuration Tab for Versal Adaptive SoCs
JESD204 PHY Configuration Tab for UltraScale+/UltraScale Devices
User Parameters
Output Generation
Transceiver Sharing for UltraScale+/UltraScale Devices
Block Automation (For Versal Adaptive SoC Only)
Connecting to Transceivers Using Block Automation for Versal Adaptive SoCs
Block Automation Output
Example 1
Example 2
GT Wizard Subsystem (For Versal Adaptive SoC only)
Configuring the JESD204 PHY in IP Integrator for UltraScale+/UltraScale Devices
Combining Multiple JESD204C Cores
Using Multiple JESD204C Cores to Connect to One or More ADCs Across SLR Boundaries
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Test Bench
Upgrading
Upgrading from v3.0 to v4.0
Upgrading from v2.0 to v3.0
Upgrading from v1.0 to v2.0
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Simulation Debug
Hardware Debug
General Checks
Issues Obtaining Lane Synchronization
Interface Debug
AXI4-Lite Interfaces
AXI4-Stream Interfaces
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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