Transmit Latency - 4.2 English

JESD204C LogiCORE IP Product Guide (PG242)

Document ID

PG242

Release Date

2023-11-06

Version

4.2 English

The latency variation is critical for JESD204C systems. The transmit latency through the IP core is fixed but the transceiver introduces some variation as the internal transmit elastic buffer of the transceiver is included in the data path.

The 8B10B and 64B66B transmit data path latencies are shown in the following tables, respectively. They do not include the latency through the JESD204_PHY IP core if using UltraScale/UltraScale+, or the GT Quad if using Versal adaptive SoCs (GT_delay).

If using UltraScale or UltraScale+ the transmit latency through the JESD204_PHY IP core is equal to the latency through the GT (GT_delay). There is no additional latency added by the JESD204_PHY IP core. Refer to the relevant GT for the PHY latency values.

Table 1. 8B10B Transmit Data Path Latency Through JESD204C
	GTME5 Transceiver	All Other Transceivers
T_TXLEMC (octet clks)	28	24
T_TXOUT	T_TXLEMC + GT_delay	T_TXLEMC + GT_delay
T_TXIN	0	0
Latency values are given in 8b10b octet clocks. See TX End to End Latency for detailed use. When using Versal adaptive SoC GTME5 transceivers, there is an additional latency through the receive data path because the 8B10B encoding function is performed external to the GT Quad.

Table 2. 64B66B Transmit Data Path Latency Through JESD204C
	GTME5 Transceiver		All Other Transceivers
	With FEC	Without FEC	With FEC	Without FEC
T_TXLEMC (core clks)	16 +/-1	14 +/-1	8	6
T_TXOUT	T_TXLEMC + GT_delay	T_TXLEMC + GT_delay	T_TXLEMC + GT_delay	T_TXLEMC + GT_delay
T_TXIN	0	0	0	0
Latency values are given in core clock cycles. See TX End to End Latency for detailed use. When using Versal adaptive SoC GTME5 transceivers there is an additional latency through the receive data path because the 64b66b encoding function is performed external to the GT Quad. When using Versal adaptive SoC GTME5 transceivers, there is an additional +/-1 clock cycle of uncertainty due to the clock crossing from the `tx_core_clk` to the `txusrclk` within the 64B66B encoder gearbox.