The JESD204_PHY core (see JESD204 PHY LogiCORE IP Product Guide (PG198)) provides a simple way to share transceivers between JESD204C cores. Any number of JESD204_PHY cores can be connected to any number of JESD204C cores to cater for any combination of ADCs and DACs using different line rates, lane counts, linecoding, and versions of the JESD204 standard.
An example of a two lane 64B66B TX and two lane 8B10B RX sharing a JESD204
PHY is shown in the following figure. The transmitter and the receiver are configured
for different line rates. Separate refclk inputs are
provided for each PLL and separate core clocks are provided for TX and RX to support
subclass 1 .
Figure 1. Transceiver Sharing for UltraScale+/UltraScale Devices
