For Subclass 0 only operation, the timing limitations imposed to support deterministic latency are removed, and a simplified clocking arrangement can be used which requires only a reference clock input. In this case, the transceiver PLL is used to generate the core clock signal. In this configuration, any clock frequency that is suitable to use as the transceiver reference cock is acceptable.
The Versal adaptive SoCs and UltraScale+/UltraScale device configurations are shown in the following figures.
This configuration is not suitable for subclass 1 or 2 operation because the output phase of the transceiver PLL is unknown, and therefore, this clock cannot be used to reliably sample SYSREF or SYNC.
Figure 1. Transceiver Output Clock Used as Core Clock (Subclass 0) for Versal Adaptive SoCs
Figure 2. Transceiver Output Clock Used as Core Clock (Subclass 0) for
UltraScale+/UltraScale Devices